mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 18:54:02 +01:00
cc12b285b6
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
118 lines
4.8 KiB
YAML
118 lines
4.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-fold-operands -o - %s | FileCheck %s
|
|
|
|
# This was attempting to look back through the REG_SEQUENCE source
|
|
# operands and trying to look for physreg defs.
|
|
|
|
---
|
|
name: fold_reg_sequence_of_copy_from_physreg_0
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo:
|
|
isEntryFunction: true
|
|
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
|
|
stackPtrOffsetReg: '$sgpr32'
|
|
occupancy: 8
|
|
body: |
|
|
bb.0:
|
|
; CHECK-LABEL: name: fold_reg_sequence_of_copy_from_physreg_0
|
|
; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
; CHECK: $vgpr1 = V_MOV_B32_e32 1, implicit $exec
|
|
; CHECK: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
|
|
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
|
|
; CHECK: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
|
|
; CHECK: FLAT_STORE_DWORDX2 killed [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
|
|
; CHECK: S_ENDPGM 0
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
$vgpr1 = V_MOV_B32_e32 1, implicit $exec
|
|
S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
|
|
%0:vgpr_32 = COPY $vgpr0
|
|
%1:vgpr_32 = COPY $vgpr1
|
|
%2:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
|
|
%3:vreg_64_align2 = IMPLICIT_DEF
|
|
FLAT_STORE_DWORDX2 killed %3, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
|
|
S_ENDPGM 0
|
|
|
|
...
|
|
|
|
---
|
|
name: fold_reg_sequence_of_copy_from_physreg_1
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo:
|
|
isEntryFunction: true
|
|
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
|
|
stackPtrOffsetReg: '$sgpr32'
|
|
occupancy: 8
|
|
body: |
|
|
bb.0:
|
|
; CHECK-LABEL: name: fold_reg_sequence_of_copy_from_physreg_1
|
|
; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
; CHECK: $vgpr1 = V_MOV_B32_e32 1, implicit $exec
|
|
; CHECK: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
|
|
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
|
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
|
|
; CHECK: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
|
|
; CHECK: FLAT_STORE_DWORDX2 killed [[REG_SEQUENCE]], killed [[DEF]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
|
|
; CHECK: S_ENDPGM 0
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
$vgpr1 = V_MOV_B32_e32 1, implicit $exec
|
|
S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
|
|
%0:vgpr_32 = COPY $vgpr0
|
|
%1:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
|
|
%2:vgpr_32 = COPY %0
|
|
%3:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %2, %subreg.sub1
|
|
%4:vreg_64_align2 = IMPLICIT_DEF
|
|
FLAT_STORE_DWORDX2 killed %3, killed %4, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
|
|
S_ENDPGM 0
|
|
|
|
...
|
|
|
|
---
|
|
name: fold_reg_sequence_of_copy_from_physreg_2
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo:
|
|
isEntryFunction: true
|
|
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
|
|
stackPtrOffsetReg: '$sgpr32'
|
|
occupancy: 8
|
|
body: |
|
|
bb.0:
|
|
; CHECK-LABEL: name: fold_reg_sequence_of_copy_from_physreg_2
|
|
; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
; CHECK: $vgpr1 = V_MOV_B32_e32 1, implicit $exec
|
|
; CHECK: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
|
|
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
|
|
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[COPY]], %subreg.sub1
|
|
; CHECK: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
|
|
; CHECK: FLAT_STORE_DWORDX2 killed [[DEF]], killed [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
|
|
; CHECK: S_ENDPGM 0
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
$vgpr1 = V_MOV_B32_e32 1, implicit $exec
|
|
S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1
|
|
%0:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
|
|
%1:vgpr_32 = COPY $vgpr0
|
|
%2:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
|
|
%3:vreg_64_align2 = IMPLICIT_DEF
|
|
FLAT_STORE_DWORDX2 killed %3, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
|
|
S_ENDPGM 0
|
|
|
|
...
|
|
|
|
# This would crash looking for a def in any mayLoad instruction
|
|
---
|
|
name: fold_inlineasm_def
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
|
|
; CHECK-LABEL: name: fold_inlineasm_def
|
|
; CHECK: INLINEASM &"s_waitcnt vmcnt($0)", 41 /* sideeffect mayload isconvergent attdialect */, 13 /* imm */, 0
|
|
; CHECK: S_ENDPGM 0
|
|
INLINEASM &"s_waitcnt vmcnt($0)", 41 /* sideeffect mayload isconvergent attdialect */, 13 /* imm */, 0
|
|
S_ENDPGM 0
|
|
|
|
...
|