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https://github.com/RPCS3/llvm-mirror.git
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6aafd76482
This patch adds a DAG combine fold for a sext(masked_load) into a sign extended masked load. Differential Revision: https://reviews.llvm.org/D84332
103 lines
4.0 KiB
LLVM
103 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs -o - %s | FileCheck %s
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define arm_aapcs_vfpcc <4 x float> @foo_v4i16(<4 x i16>* nocapture readonly %pSrc, i32 %blockSize, <4 x i16> %a) {
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; CHECK-LABEL: foo_v4i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: vpt.s32 lt, q0, zr
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; CHECK-NEXT: vldrht.s32 q0, [r0]
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; CHECK-NEXT: vcvt.f32.s32 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%active.lane.mask = icmp slt <4 x i16> %a, zeroinitializer
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%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %pSrc, i32 2, <4 x i1> %active.lane.mask, <4 x i16> undef)
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%0 = sitofp <4 x i16> %wide.masked.load to <4 x float>
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ret <4 x float> %0
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}
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define arm_aapcs_vfpcc <8 x half> @foo_v8i8(<8 x i8>* nocapture readonly %pSrc, i32 %blockSize, <8 x i8> %a) {
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; CHECK-LABEL: foo_v8i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s8 q0, q0
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; CHECK-NEXT: vpt.s16 lt, q0, zr
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; CHECK-NEXT: vldrbt.s16 q0, [r0]
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; CHECK-NEXT: vcvt.f16.s16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%active.lane.mask = icmp slt <8 x i8> %a, zeroinitializer
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%wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %pSrc, i32 1, <8 x i1> %active.lane.mask, <8 x i8> undef)
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%0 = sitofp <8 x i8> %wide.masked.load to <8 x half>
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <4 x float> @foo_v4i8(<4 x i8>* nocapture readonly %pSrc, i32 %blockSize, <4 x i8> %a) {
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; CHECK-LABEL: foo_v4i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s8 q0, q0
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: vpt.s32 lt, q0, zr
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; CHECK-NEXT: vldrbt.s32 q0, [r0]
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; CHECK-NEXT: vcvt.f32.s32 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%active.lane.mask = icmp slt <4 x i8> %a, zeroinitializer
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%wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %pSrc, i32 1, <4 x i1> %active.lane.mask, <4 x i8> undef)
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%0 = sitofp <4 x i8> %wide.masked.load to <4 x float>
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ret <4 x float> %0
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}
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define arm_aapcs_vfpcc <4 x double> @foo_v4i32(<4 x i32>* nocapture readonly %pSrc, i32 %blockSize, <4 x i32> %a) {
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; CHECK-LABEL: foo_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
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; CHECK-NEXT: vpt.s32 lt, q0, zr
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; CHECK-NEXT: vldrwt.u32 q5, [r0]
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; CHECK-NEXT: vmov.f64 d8, d10
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; CHECK-NEXT: vmov.f32 s18, s21
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; CHECK-NEXT: vmov r0, s18
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; CHECK-NEXT: asrs r1, r0, #31
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; CHECK-NEXT: bl __aeabi_l2d
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; CHECK-NEXT: vmov r2, s16
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; CHECK-NEXT: vmov d9, r0, r1
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; CHECK-NEXT: asrs r3, r2, #31
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: mov r1, r3
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; CHECK-NEXT: bl __aeabi_l2d
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; CHECK-NEXT: vmov.f64 d12, d11
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; CHECK-NEXT: vmov.f32 s26, s23
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; CHECK-NEXT: vmov d8, r0, r1
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; CHECK-NEXT: vmov r2, s26
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; CHECK-NEXT: asrs r3, r2, #31
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: mov r1, r3
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; CHECK-NEXT: bl __aeabi_l2d
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; CHECK-NEXT: vmov r2, s24
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; CHECK-NEXT: vmov d11, r0, r1
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; CHECK-NEXT: asrs r3, r2, #31
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: mov r1, r3
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; CHECK-NEXT: bl __aeabi_l2d
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; CHECK-NEXT: vmov d10, r0, r1
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; CHECK-NEXT: vmov q0, q4
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; CHECK-NEXT: vmov q1, q5
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%active.lane.mask = icmp slt <4 x i32> %a, zeroinitializer
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%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %pSrc, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
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%0 = sitofp <4 x i32> %wide.masked.load to <4 x double>
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ret <4 x double> %0
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}
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declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
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declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>)
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declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32 immarg, <4 x i1>, <4 x i8>)
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declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
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