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Coalescing can remove copy-like instructions with sub-register operands that constrained the register class. Examples are: x86: GR32_ABCD:sub_8bit_hi -> GR32 arm: DPR_VFP2:ssub0 -> DPR Recompute the register class of any virtual registers that are used by less instructions after coalescing. This affects code generation for the Cortex-A8 where we use NEON instructions for f32 operations, c.f. fp_convert.ll: vadd.f32 d16, d1, d0 vcvt.s32.f32 d0, d16 The register allocator is now free to use d16 for the temporary, and that comes first in the allocation order because it doesn't interfere with any s-registers. llvm-svn: 137133
51 lines
1.2 KiB
LLVM
51 lines
1.2 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=VFP2
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; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON
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; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
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define i32 @test1(float %a, float %b) {
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; VFP2: test1:
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; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
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; NEON: test1:
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; NEON: vadd.f32 [[D0:d[0-9]+]]
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; NEON: vcvt.s32.f32 d0, [[D0]]
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entry:
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%0 = fadd float %a, %b
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%1 = fptosi float %0 to i32
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ret i32 %1
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}
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define i32 @test2(float %a, float %b) {
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; VFP2: test2:
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; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
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; NEON: test2:
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; NEON: vadd.f32 [[D0:d[0-9]+]]
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; NEON: vcvt.u32.f32 d0, [[D0]]
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entry:
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%0 = fadd float %a, %b
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%1 = fptoui float %0 to i32
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ret i32 %1
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}
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define float @test3(i32 %a, i32 %b) {
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; VFP2: test3:
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; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
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; NEON: test3:
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; NEON: vcvt.f32.u32 d0, d0
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entry:
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%0 = add i32 %a, %b
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%1 = uitofp i32 %0 to float
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ret float %1
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}
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define float @test4(i32 %a, i32 %b) {
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; VFP2: test4:
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; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
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; NEON: test4:
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; NEON: vcvt.f32.s32 d0, d0
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entry:
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%0 = add i32 %a, %b
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%1 = sitofp i32 %0 to float
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ret float %1
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}
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