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llvm-mirror/test/CodeGen/ARM/fp_convert.ll

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Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81293
2009-09-09 02:09:15 +02:00
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
switch the flag for using NEON for SP floating point to a subtarget 'feature'. Re-commit. This time complete with testsuite updates. llvm-svn: 99570
2010-03-26 00:47:34 +01:00
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=VFP2
Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81293
2009-09-09 02:09:15 +02:00
; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON
; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
now that these are in file-check format, we can merge them together into one bigger test (which runs faster) llvm-svn: 78672
2009-08-11 17:54:17 +02:00
define i32 @test1(float %a, float %b) {
; VFP2: test1:
Avoid write-after-write issue hazards for Cortex-A9. Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. llvm-svn: 129772
2011-04-19 20:11:45 +02:00
; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
now that these are in file-check format, we can merge them together into one bigger test (which runs faster) llvm-svn: 78672
2009-08-11 17:54:17 +02:00
; NEON: test1:
Inflate register classes after coalescing. Coalescing can remove copy-like instructions with sub-register operands that constrained the register class. Examples are: x86: GR32_ABCD:sub_8bit_hi -> GR32 arm: DPR_VFP2:ssub0 -> DPR Recompute the register class of any virtual registers that are used by less instructions after coalescing. This affects code generation for the Cortex-A8 where we use NEON instructions for f32 operations, c.f. fp_convert.ll: vadd.f32 d16, d1, d0 vcvt.s32.f32 d0, d16 The register allocator is now free to use d16 for the temporary, and that comes first in the allocation order because it doesn't interfere with any s-registers. llvm-svn: 137133
2011-08-09 20:19:41 +02:00
; NEON: vadd.f32 [[D0:d[0-9]+]]
; NEON: vcvt.s32.f32 d0, [[D0]]
now that these are in file-check format, we can merge them together into one bigger test (which runs faster) llvm-svn: 78672
2009-08-11 17:54:17 +02:00
entry:
%0 = fadd float %a, %b
%1 = fptosi float %0 to i32
ret i32 %1
}
define i32 @test2(float %a, float %b) {
; VFP2: test2:
Avoid write-after-write issue hazards for Cortex-A9. Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. llvm-svn: 129772
2011-04-19 20:11:45 +02:00
; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
now that these are in file-check format, we can merge them together into one bigger test (which runs faster) llvm-svn: 78672
2009-08-11 17:54:17 +02:00
; NEON: test2:
Inflate register classes after coalescing. Coalescing can remove copy-like instructions with sub-register operands that constrained the register class. Examples are: x86: GR32_ABCD:sub_8bit_hi -> GR32 arm: DPR_VFP2:ssub0 -> DPR Recompute the register class of any virtual registers that are used by less instructions after coalescing. This affects code generation for the Cortex-A8 where we use NEON instructions for f32 operations, c.f. fp_convert.ll: vadd.f32 d16, d1, d0 vcvt.s32.f32 d0, d16 The register allocator is now free to use d16 for the temporary, and that comes first in the allocation order because it doesn't interfere with any s-registers. llvm-svn: 137133
2011-08-09 20:19:41 +02:00
; NEON: vadd.f32 [[D0:d[0-9]+]]
; NEON: vcvt.u32.f32 d0, [[D0]]
now that these are in file-check format, we can merge them together into one bigger test (which runs faster) llvm-svn: 78672
2009-08-11 17:54:17 +02:00
entry:
%0 = fadd float %a, %b
%1 = fptoui float %0 to i32
ret i32 %1
}
define float @test3(i32 %a, i32 %b) {
; VFP2: test3:
Avoid write-after-write issue hazards for Cortex-A9. Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. llvm-svn: 129772
2011-04-19 20:11:45 +02:00
; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
now that these are in file-check format, we can merge them together into one bigger test (which runs faster) llvm-svn: 78672
2009-08-11 17:54:17 +02:00
; NEON: test3:
; NEON: vcvt.f32.u32 d0, d0
entry:
%0 = add i32 %a, %b
%1 = uitofp i32 %0 to float
ret float %1
}
define float @test4(i32 %a, i32 %b) {
; VFP2: test4:
Avoid write-after-write issue hazards for Cortex-A9. Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. llvm-svn: 129772
2011-04-19 20:11:45 +02:00
; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
now that these are in file-check format, we can merge them together into one bigger test (which runs faster) llvm-svn: 78672
2009-08-11 17:54:17 +02:00
; NEON: test4:
; NEON: vcvt.f32.s32 d0, d0
entry:
%0 = add i32 %a, %b
%1 = sitofp i32 %0 to float
ret float %1
}
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