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llvm-mirror/lib/Target/AArch64
Arlo Siemsen d4eefe6819 Add ehcont section support
In the future Windows will enable Control-flow Enforcement Technology (CET aka shadow stacks). To protect the path where the context is updated during exception handling, the binary is required to enumerate valid unwind entrypoints in a dedicated section which is validated when the context is being set during exception handling.

This change allows llvm to generate the section that contains the appropriate symbol references in the form expected by the msvc linker.

This feature is enabled through a new module flag, ehcontguard, which was modelled on the cfguard flag.

The change includes a test that when the module flag is enabled the section is correctly generated.

The set of exception continuation information includes returns from exceptional control flow (catchret in llvm).

In order to collect catchret we:
1) Includes an additional flag on machine basic blocks to indicate that the given block is the target of a catchret operation,
2) Introduces a new machine function pass to insert and collect symbols at the start of each block, and
3) Combines these targets with the other EHCont targets that were already being collected.

Change originally authored by Daniel Frampton <dframpto@microsoft.com>

For more details, see MSVC documentation for `/guard:ehcont`
  https://docs.microsoft.com/en-us/cpp/build/reference/guard-enable-eh-continuation-metadata

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D94835
2021-02-15 14:27:12 +08:00
..
AsmParser [AArch64AsmParser] Fix type-limits warning for VectorIndex. 2021-02-08 15:35:30 +00:00
Disassembler [AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension 2020-12-17 13:46:23 +00:00
GISel [AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE 2021-02-12 14:55:15 -08:00
MCTargetDesc [AArch64][SVE] Asm: Fix supported immediates for DUP/CPY 2021-02-11 08:14:15 +00:00
TargetInfo llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
Utils [ARM][AArch64] Adding basic support for the v8.7-A architecture 2020-12-17 13:45:08 +00:00
AArch64.h [AArch64] Homogeneous Prolog and Epilog Size Optimization 2021-02-02 14:57:26 -08:00
AArch64.td [AArch64] Add Cortex CPU subtarget features for instruction fusion. 2021-01-25 09:11:29 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp Add ehcont section support 2021-02-15 14:27:12 +08:00
AArch64BranchTargets.cpp
AArch64CallingConvention.cpp [SVE] Deal with SVE tuple call arguments correctly when running out of registers 2020-11-12 08:41:50 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64Combine.td [AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE 2021-02-12 14:55:15 -08:00
AArch64CompressJumpTables.cpp [AArch64] Don't try to compress jump tables if there are any inline asm instructions. 2020-12-10 12:20:02 -08:00
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandImm.cpp
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp AArch64: use a constpool for blockaddress(...) on MachO 2021-02-08 15:13:29 +00:00
AArch64FalkorHWPFFix.cpp
AArch64FastISel.cpp
AArch64FrameLowering.cpp [AArch64] Homogeneous Prolog and Epilog Size Optimization 2021-02-02 14:57:26 -08:00
AArch64FrameLowering.h [AArch64] Homogeneous Prolog and Epilog Size Optimization 2021-02-02 14:57:26 -08:00
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td
AArch64InstrFormats.td [AArch64] Adding Neon Sm3 & Sm4 Intrinsics 2021-02-11 14:20:20 -08:00
AArch64InstrGISel.td [AArch64][GlobalISel] Add selection support for fpr bank source variants of G_SITOFP and G_UITOFP. 2021-01-14 19:31:19 -08:00
AArch64InstrInfo.cpp [GlobalISel] Propagate extends through G_PHIs into the incoming value blocks. 2021-02-12 11:52:52 -08:00
AArch64InstrInfo.h [GlobalISel] Propagate extends through G_PHIs into the incoming value blocks. 2021-02-12 11:52:52 -08:00
AArch64InstrInfo.td [AArch64] Adding Neon Sm3 & Sm4 Intrinsics 2021-02-11 14:20:20 -08:00
AArch64ISelDAGToDAG.cpp [AArch64] Adding ACLE intrinsics for the LS64 extension 2021-01-14 09:43:58 +00:00
AArch64ISelLowering.cpp [ObjC][ARC] Use operand bundle 'clang.arc.attachedcall' instead of 2021-02-12 09:51:57 -08:00
AArch64ISelLowering.h [TargetLowering] Use Align in allowsMisalignedMemoryAccesses. 2021-02-04 19:22:06 -08:00
AArch64LoadStoreOptimizer.cpp [AArch64] Don't merge sp decrement into later stores when using WinCFI 2020-10-01 19:03:27 +03:00
AArch64LowerHomogeneousPrologEpilog.cpp AArch64LowerHomogeneousPrologEpilog.cpp - fix Wdocumentation warning. NFCI. 2021-02-05 11:34:43 +00:00
AArch64MachineFunctionInfo.cpp
AArch64MachineFunctionInfo.h [AArch64][SVE] Allow accesses to SVE stack objects to use frame pointer 2021-01-28 12:39:57 +00:00
AArch64MacroFusion.cpp [AArch64] Add Cortex CPU subtarget features for instruction fusion. 2021-01-25 09:11:29 +00:00
AArch64MacroFusion.h [llvm] Add missing header guards (NFC) 2021-01-30 09:53:42 -08:00
AArch64MCInstLower.cpp [AArch64] [Windows] Properly add :lo12: reloc specifiers when generating assembly 2021-01-12 23:56:03 +02:00
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp [AArch64] Fix Copy Elemination for negative values 2020-12-18 13:30:46 +00:00
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp Change materializeFrameBaseRegister() to return register 2021-01-22 15:51:06 -08:00
AArch64RegisterInfo.h Change materializeFrameBaseRegister() to return register 2021-01-22 15:51:06 -08:00
AArch64RegisterInfo.td [AArch64] Add a GPR64x8 register class 2020-12-17 13:45:46 +00:00
AArch64SchedA53.td
AArch64SchedA55.td [AArch64] Enable Cortex-A55 schedmodel 2020-11-30 19:28:34 +00:00
AArch64SchedA57.td [AARCH64] Improve accumulator forwarding for Cortex-A57 model 2021-01-04 10:58:43 +00:00
AArch64SchedA57WriteRes.td [AARCH64] Improve accumulator forwarding for Cortex-A57 model 2021-01-04 10:58:43 +00:00
AArch64SchedA64FX.td [AArch64] Add Fujitsu A64FX scheduling model 2021-01-15 17:14:04 +09:00
AArch64SchedCyclone.td
AArch64SchedExynosM3.td
AArch64SchedExynosM4.td
AArch64SchedExynosM5.td
AArch64SchedFalkor.td
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td
AArch64SchedPredicates.td
AArch64SchedThunderX2T99.td
AArch64SchedThunderX3T110.td
AArch64SchedThunderX.td
AArch64SchedTSV110.td [AArch64] Add pipeline model for HiSilicon's TSV110 2020-11-07 01:23:00 +03:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp [AArch64] reuse another map iterator. NFC 2020-09-28 11:30:21 -07:00
AArch64SLSHardening.cpp
AArch64SpeculationHardening.cpp
AArch64StackTagging.cpp [llvm] Use llvm::lower_bound and llvm::upper_bound (NFC) 2021-01-05 21:15:59 -08:00
AArch64StackTaggingPreRA.cpp [MTE] Pin the tagged base pointer to one of the stack slots. 2020-10-15 12:50:16 -07:00
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp AArch64: add apple-a14 as a CPU 2021-01-19 14:04:53 +00:00
AArch64Subtarget.h [AArch64] Add Cortex CPU subtarget features for instruction fusion. 2021-01-25 09:11:29 +00:00
AArch64SVEInstrInfo.td [SVE] Restrict the usage of REINTERPRET_CAST. 2021-01-15 11:32:13 +00:00
AArch64SystemOperands.td [AArch64] Add +pauth archictecture option, allowing the v8.3a pointer authentication extension. 2021-01-08 13:21:11 +00:00
AArch64TargetMachine.cpp Add ehcont section support 2021-02-15 14:27:12 +08:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp [Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics 2021-02-12 08:13:50 -05:00
AArch64TargetTransformInfo.h [Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics 2021-02-12 08:13:50 -05:00
CMakeLists.txt [AArch64] Homogeneous Prolog and Epilog Size Optimization 2021-02-02 14:57:26 -08:00
SVEInstrFormats.td [AArch64] Correct some tablegen operand types. NFC 2021-02-06 14:34:14 +00:00
SVEIntrinsicOpts.cpp [AArch64][SVE] Coalesce ptrue instrinsic calls where possible 2021-02-05 10:43:28 +00:00