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2529cb73ff
This patch implements out of line atomics for LSE deployment mechanism. Details how it works can be found in llvm/docs/Atomics.rst Options -moutline-atomics and -mno-outline-atomics to enable and disable it were added to clang driver. This is clang and llvm part of out-of-line atomics interface, library part is already supported by libgcc. Compiler-rt support is provided in separate patch. Differential Revision: https://reviews.llvm.org/D91157
264 lines
6.7 KiB
LLVM
264 lines
6.7 KiB
LLVM
; RUN: llc -mtriple=arm64_32-apple-ios7.0 -o - %s | FileCheck %s
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; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS
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define i8 @test_load_8(i8* %addr) {
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; CHECK-LABAL: test_load_8:
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; CHECK: ldarb w0, [x0]
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%val = load atomic i8, i8* %addr seq_cst, align 1
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ret i8 %val
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}
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define i16 @test_load_16(i16* %addr) {
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; CHECK-LABAL: test_load_16:
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; CHECK: ldarh w0, [x0]
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%val = load atomic i16, i16* %addr acquire, align 2
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ret i16 %val
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}
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define i32 @test_load_32(i32* %addr) {
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; CHECK-LABAL: test_load_32:
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; CHECK: ldar w0, [x0]
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%val = load atomic i32, i32* %addr seq_cst, align 4
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ret i32 %val
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}
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define i64 @test_load_64(i64* %addr) {
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; CHECK-LABAL: test_load_64:
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; CHECK: ldar x0, [x0]
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%val = load atomic i64, i64* %addr seq_cst, align 8
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ret i64 %val
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}
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define i8* @test_load_ptr(i8** %addr) {
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; CHECK-LABAL: test_load_ptr:
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; CHECK: ldar w0, [x0]
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%val = load atomic i8*, i8** %addr seq_cst, align 8
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ret i8* %val
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}
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define void @test_store_8(i8* %addr) {
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; CHECK-LABAL: test_store_8:
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; CHECK: stlrb wzr, [x0]
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store atomic i8 0, i8* %addr seq_cst, align 1
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ret void
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}
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define void @test_store_16(i16* %addr) {
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; CHECK-LABAL: test_store_16:
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; CHECK: stlrh wzr, [x0]
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store atomic i16 0, i16* %addr seq_cst, align 2
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ret void
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}
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define void @test_store_32(i32* %addr) {
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; CHECK-LABAL: test_store_32:
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; CHECK: stlr wzr, [x0]
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store atomic i32 0, i32* %addr seq_cst, align 4
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ret void
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}
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define void @test_store_64(i64* %addr) {
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; CHECK-LABAL: test_store_64:
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; CHECK: stlr xzr, [x0]
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store atomic i64 0, i64* %addr seq_cst, align 8
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ret void
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}
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define void @test_store_ptr(i8** %addr) {
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; CHECK-LABAL: test_store_ptr:
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; CHECK: stlr wzr, [x0]
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store atomic i8* null, i8** %addr seq_cst, align 8
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ret void
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}
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declare i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
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declare i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
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declare i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
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declare i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
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define i8 @test_ldxr_8(i8* %addr) {
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; CHECK-LABEL: test_ldxr_8:
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; CHECK: ldxrb w0, [x0]
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%val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
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%val8 = trunc i64 %val to i8
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ret i8 %val8
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}
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define i16 @test_ldxr_16(i16* %addr) {
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; CHECK-LABEL: test_ldxr_16:
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; CHECK: ldxrh w0, [x0]
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%val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
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%val16 = trunc i64 %val to i16
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ret i16 %val16
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}
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define i32 @test_ldxr_32(i32* %addr) {
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; CHECK-LABEL: test_ldxr_32:
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; CHECK: ldxr w0, [x0]
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%val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
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%val32 = trunc i64 %val to i32
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ret i32 %val32
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}
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define i64 @test_ldxr_64(i64* %addr) {
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; CHECK-LABEL: test_ldxr_64:
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; CHECK: ldxr x0, [x0]
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%val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
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ret i64 %val
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}
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declare i64 @llvm.aarch64.ldaxr.p0i8(i8* %addr)
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declare i64 @llvm.aarch64.ldaxr.p0i16(i16* %addr)
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declare i64 @llvm.aarch64.ldaxr.p0i32(i32* %addr)
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declare i64 @llvm.aarch64.ldaxr.p0i64(i64* %addr)
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define i8 @test_ldaxr_8(i8* %addr) {
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; CHECK-LABEL: test_ldaxr_8:
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; CHECK: ldaxrb w0, [x0]
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%val = call i64 @llvm.aarch64.ldaxr.p0i8(i8* %addr)
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%val8 = trunc i64 %val to i8
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ret i8 %val8
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}
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define i16 @test_ldaxr_16(i16* %addr) {
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; CHECK-LABEL: test_ldaxr_16:
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; CHECK: ldaxrh w0, [x0]
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%val = call i64 @llvm.aarch64.ldaxr.p0i16(i16* %addr)
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%val16 = trunc i64 %val to i16
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ret i16 %val16
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}
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define i32 @test_ldaxr_32(i32* %addr) {
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; CHECK-LABEL: test_ldaxr_32:
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; CHECK: ldaxr w0, [x0]
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%val = call i64 @llvm.aarch64.ldaxr.p0i32(i32* %addr)
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%val32 = trunc i64 %val to i32
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ret i32 %val32
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}
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define i64 @test_ldaxr_64(i64* %addr) {
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; CHECK-LABEL: test_ldaxr_64:
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; CHECK: ldaxr x0, [x0]
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%val = call i64 @llvm.aarch64.ldaxr.p0i64(i64* %addr)
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ret i64 %val
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}
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declare i32 @llvm.aarch64.stxr.p0i8(i64, i8*)
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declare i32 @llvm.aarch64.stxr.p0i16(i64, i16*)
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declare i32 @llvm.aarch64.stxr.p0i32(i64, i32*)
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declare i32 @llvm.aarch64.stxr.p0i64(i64, i64*)
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define i32 @test_stxr_8(i8* %addr, i8 %val) {
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; CHECK-LABEL: test_stxr_8:
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; CHECK: stxrb [[TMP:w[0-9]+]], w1, [x0]
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; CHECK: mov w0, [[TMP]]
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%extval = zext i8 %val to i64
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%success = call i32 @llvm.aarch64.stxr.p0i8(i64 %extval, i8* %addr)
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ret i32 %success
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}
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define i32 @test_stxr_16(i16* %addr, i16 %val) {
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; CHECK-LABEL: test_stxr_16:
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; CHECK: stxrh [[TMP:w[0-9]+]], w1, [x0]
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; CHECK: mov w0, [[TMP]]
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%extval = zext i16 %val to i64
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%success = call i32 @llvm.aarch64.stxr.p0i16(i64 %extval, i16* %addr)
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ret i32 %success
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}
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define i32 @test_stxr_32(i32* %addr, i32 %val) {
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; CHECK-LABEL: test_stxr_32:
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; CHECK: stxr [[TMP:w[0-9]+]], w1, [x0]
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; CHECK: mov w0, [[TMP]]
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%extval = zext i32 %val to i64
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%success = call i32 @llvm.aarch64.stxr.p0i32(i64 %extval, i32* %addr)
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ret i32 %success
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}
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define i32 @test_stxr_64(i64* %addr, i64 %val) {
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; CHECK-LABEL: test_stxr_64:
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; CHECK: stxr [[TMP:w[0-9]+]], x1, [x0]
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; CHECK: mov w0, [[TMP]]
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%success = call i32 @llvm.aarch64.stxr.p0i64(i64 %val, i64* %addr)
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ret i32 %success
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}
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declare i32 @llvm.aarch64.stlxr.p0i8(i64, i8*)
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declare i32 @llvm.aarch64.stlxr.p0i16(i64, i16*)
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declare i32 @llvm.aarch64.stlxr.p0i32(i64, i32*)
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declare i32 @llvm.aarch64.stlxr.p0i64(i64, i64*)
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define i32 @test_stlxr_8(i8* %addr, i8 %val) {
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; CHECK-LABEL: test_stlxr_8:
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; CHECK: stlxrb [[TMP:w[0-9]+]], w1, [x0]
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; CHECK: mov w0, [[TMP]]
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%extval = zext i8 %val to i64
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%success = call i32 @llvm.aarch64.stlxr.p0i8(i64 %extval, i8* %addr)
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ret i32 %success
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}
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define i32 @test_stlxr_16(i16* %addr, i16 %val) {
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; CHECK-LABEL: test_stlxr_16:
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; CHECK: stlxrh [[TMP:w[0-9]+]], w1, [x0]
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; CHECK: mov w0, [[TMP]]
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%extval = zext i16 %val to i64
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%success = call i32 @llvm.aarch64.stlxr.p0i16(i64 %extval, i16* %addr)
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ret i32 %success
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}
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define i32 @test_stlxr_32(i32* %addr, i32 %val) {
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; CHECK-LABEL: test_stlxr_32:
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; CHECK: stlxr [[TMP:w[0-9]+]], w1, [x0]
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; CHECK: mov w0, [[TMP]]
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%extval = zext i32 %val to i64
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%success = call i32 @llvm.aarch64.stlxr.p0i32(i64 %extval, i32* %addr)
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ret i32 %success
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}
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define i32 @test_stlxr_64(i64* %addr, i64 %val) {
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; CHECK-LABEL: test_stlxr_64:
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; CHECK: stlxr [[TMP:w[0-9]+]], x1, [x0]
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; CHECK: mov w0, [[TMP]]
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%success = call i32 @llvm.aarch64.stlxr.p0i64(i64 %val, i64* %addr)
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ret i32 %success
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}
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define {i8*, i1} @test_cmpxchg_ptr(i8** %addr, i8* %cmp, i8* %new) {
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; OUTLINE-ATOMICS: bl ___aarch64_cas4_acq_rel
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; CHECK-LABEL: test_cmpxchg_ptr:
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; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxr [[OLD:w[0-9]+]], [x0]
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; CHECK: cmp [[OLD]], w1
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; CHECK: b.ne [[DONE:LBB[0-9]+_[0-9]+]]
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; CHECK: stlxr [[SUCCESS:w[0-9]+]], w2, [x0]
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; CHECK: cbnz [[SUCCESS]], [[LOOP]]
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; CHECK: mov w1, #1
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; CHECK: mov w0, [[OLD]]
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; CHECK: ret
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; CHECK: [[DONE]]:
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; CHECK: clrex
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; CHECK: mov w1, wzr
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; CHECK: mov w0, [[OLD]]
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; CHECK: ret
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%res = cmpxchg i8** %addr, i8* %cmp, i8* %new acq_rel acquire
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ret {i8*, i1} %res
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}
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