Paul Walker 6d505ef4dd [SVE] Use reg+reg addressing mode for immediate offsets. ... For reg+imm SVE addressing mode imm is implictly scaled by VL, making them impractical for truely immediate offsets. However, if the offset can be unscaled based on the storage element type we can use the reg+reg SVE addressing mode and thus either reduce the number of generate add instructions or replace them with a mov instruction that can be hoisted from the hot code path. Differential Revision: https://reviews.llvm.org/D106744		2021-07-26 16:24:16 +01:00
..
AArch64	[SVE] Use reg+reg addressing mode for immediate offsets.	2021-07-26 16:24:16 +01:00
AMDGPU	[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset	2021-07-26 14:27:30 +01:00
ARC
ARM
AVR	[AVR] Only support sp, r0 and r1 in llvm.read_register	2021-07-24 14:03:27 +02:00
BPF
Generic
Hexagon
Inputs
Lanai
M68k
Mips	[llvm][sve] Lowering for VLS truncating stores	2021-07-23 14:04:55 +01:00
MIR
MSP430
NVPTX
PowerPC	[PowerPC] Implement XL compatible behavior of __compare_and_swap	2021-07-23 01:16:02 +00:00
RISCV	[SelectionDAG] Support scalable-vector splats in yet more cases	2021-07-26 10:15:08 +01:00
SPARC
SystemZ	[SystemZ] Add support for new cpu architecture - arch14	2021-07-26 16:57:28 +02:00
Thumb
Thumb2	[ARM] Ensure correct regclass in distributing postinc	2021-07-26 14:26:38 +01:00
VE
WebAssembly	[WebAssembly] Codegen for pmin and pmax	2021-07-23 14:49:21 -07:00
WinCFGuard
WinEH
X86	[X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets	2021-07-26 11:11:56 +01:00
XCore