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6449e66c97
This reverses a questionable IR canonicalization when a truncate is free: sra (add (shl X, N1C), AddC), N1C --> sext (add (trunc X to (width - N1C)), AddC') https://rise4fun.com/Alive/slRC More details in PR42644: https://bugs.llvm.org/show_bug.cgi?id=42644 I limited this to pre-legalization for code simplicity because that should be enough to reverse the IR patterns. I don't have any evidence (no regression test diffs) that we need to try this later. Differential Revision: https://reviews.llvm.org/D65607 llvm-svn: 367710
152 lines
4.0 KiB
LLVM
152 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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; Check that we optimize out AND instructions and ADD/SUB instructions
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; modulo the shift size to take advantage of the implicit mod done on
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; the shift amount value by the variable shift/rotate instructions.
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define i32 @test1(i32 %x, i64 %y) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w0, w0, w1
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; CHECK-NEXT: ret
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%sh_prom = trunc i64 %y to i32
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%shr = lshr i32 %x, %sh_prom
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ret i32 %shr
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}
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define i64 @test2(i32 %x, i64 %y) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg w[[REG:[0-9]+]], w0
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; CHECK-NEXT: asr x0, x1, x[[REG]]
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; CHECK-NEXT: ret
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%sub9 = sub nsw i32 64, %x
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%sh_prom12.i = zext i32 %sub9 to i64
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%shr.i = ashr i64 %y, %sh_prom12.i
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ret i64 %shr.i
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}
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define i64 @test3(i64 %x, i64 %y) {
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; CHECK-LABEL: test3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl x0, x1, x0
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; CHECK-NEXT: ret
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%add = add nsw i64 64, %x
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%shl = shl i64 %y, %add
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ret i64 %shl
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}
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define i64 @test4(i64 %y, i32 %s) {
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; CHECK-LABEL: test4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: asr x0, x0, x1
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; CHECK-NEXT: ret
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entry:
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%sh_prom = zext i32 %s to i64
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%shr = ashr i64 %y, %sh_prom
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ret i64 %shr
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}
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define i64 @test5(i64 %y, i32 %s) {
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; CHECK-LABEL: test5:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: asr x0, x0, x1
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; CHECK-NEXT: ret
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entry:
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%sh_prom = sext i32 %s to i64
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%shr = ashr i64 %y, %sh_prom
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ret i64 %shr
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}
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define i64 @test6(i64 %y, i32 %s) {
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; CHECK-LABEL: test6:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: lsl x0, x0, x1
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; CHECK-NEXT: ret
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entry:
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%sh_prom = sext i32 %s to i64
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%shr = shl i64 %y, %sh_prom
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ret i64 %shr
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}
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; PR42644 - https://bugs.llvm.org/show_bug.cgi?id=42644
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define i64 @ashr_add_shl_i32(i64 %r) {
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; CHECK-LABEL: ashr_add_shl_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #1 // =1
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; CHECK-NEXT: sxtw x0, w8
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; CHECK-NEXT: ret
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%conv = shl i64 %r, 32
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%sext = add i64 %conv, 4294967296
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%conv1 = ashr i64 %sext, 32
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ret i64 %conv1
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}
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define i64 @ashr_add_shl_i8(i64 %r) {
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; CHECK-LABEL: ashr_add_shl_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add w8, w0, #1 // =1
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; CHECK-NEXT: sxtb x0, w8
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; CHECK-NEXT: ret
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%conv = shl i64 %r, 56
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%sext = add i64 %conv, 72057594037927936
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%conv1 = ashr i64 %sext, 56
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ret i64 %conv1
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}
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define <4 x i32> @ashr_add_shl_v4i8(<4 x i32> %r) {
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; CHECK-LABEL: ashr_add_shl_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.4s, v0.4s, #24
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; CHECK-NEXT: movi v1.4s, #1, lsl #24
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: sshr v0.4s, v0.4s, #24
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; CHECK-NEXT: ret
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%conv = shl <4 x i32> %r, <i32 24, i32 24, i32 24, i32 24>
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%sext = add <4 x i32> %conv, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
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%conv1 = ashr <4 x i32> %sext, <i32 24, i32 24, i32 24, i32 24>
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ret <4 x i32> %conv1
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}
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define i64 @ashr_add_shl_i36(i64 %r) {
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; CHECK-LABEL: ashr_add_shl_i36:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sbfx x0, x0, #0, #28
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; CHECK-NEXT: ret
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%conv = shl i64 %r, 36
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%sext = add i64 %conv, 4294967296
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%conv1 = ashr i64 %sext, 36
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ret i64 %conv1
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}
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define i64 @ashr_add_shl_mismatch_shifts1(i64 %r) {
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; CHECK-LABEL: ashr_add_shl_mismatch_shifts1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4294967296
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; CHECK-NEXT: add x8, x8, x0, lsl #8
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; CHECK-NEXT: asr x0, x8, #32
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; CHECK-NEXT: ret
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%conv = shl i64 %r, 8
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%sext = add i64 %conv, 4294967296
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%conv1 = ashr i64 %sext, 32
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ret i64 %conv1
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}
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define i64 @ashr_add_shl_mismatch_shifts2(i64 %r) {
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; CHECK-LABEL: ashr_add_shl_mismatch_shifts2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4294967296
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; CHECK-NEXT: add x8, x8, x0, lsr #8
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; CHECK-NEXT: lsr x0, x8, #8
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; CHECK-NEXT: ret
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%conv = lshr i64 %r, 8
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%sext = add i64 %conv, 4294967296
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%conv1 = ashr i64 %sext, 8
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ret i64 %conv1
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}
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