mirror of
https://github.com/RPCS3/llvm-mirror.git
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a0a984398f
Co-Authored-by: Graham Hunter <graham.hunter@arm.com> Co-Authored-by: Paul Walker <paul.walker@arm.com> Differential Revision: https://reviews.llvm.org/D93292
476 lines
13 KiB
YAML
476 lines
13 KiB
YAML
# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
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# Test instruction sequences where PTEST is redundant and thus gets removed.
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---
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name: whilegt_b8_s32
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr32 }
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- { id: 1, class: gpr32 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: gpr32 }
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- { id: 5, class: gpr32 }
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liveins:
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- { reg: '$w0', virtual-reg: '%0' }
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- { reg: '$w1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $w0, $w1
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; Here we check the expected sequence with subsequent tests
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; just asserting there is no PTEST instruction.
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;
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; CHECK-LABEL: name: whilegt_b8_s32
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; CHECK: %3:ppr = WHILEGT_PWW_B %0, %1, implicit-def $nzcv
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; CHECK-NEXT: %4:gpr32 = COPY $wzr
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; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
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%1:gpr32 = COPY $w1
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%0:gpr32 = COPY $w0
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%2:ppr = PTRUE_B 31
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%3:ppr = WHILEGT_PWW_B %0, %1, implicit-def dead $nzcv
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PTEST_PP killed %2, killed %3, implicit-def $nzcv
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%4:gpr32 = COPY $wzr
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%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
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$w0 = COPY %5
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RET_ReallyLR implicit $w0
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...
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---
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name: whilegt_b8_s64
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64 }
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- { id: 1, class: gpr64 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: gpr32 }
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- { id: 5, class: gpr32 }
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liveins:
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- { reg: '$x0', virtual-reg: '%0' }
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- { reg: '$x1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; CHECK-LABEL: name: whilegt_b8_s64
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; CHECK-NOT: PTEST
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%1:gpr64 = COPY $x1
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%0:gpr64 = COPY $x0
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%2:ppr = PTRUE_B 31
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%3:ppr = WHILEGT_PXX_B %0, %1, implicit-def dead $nzcv
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PTEST_PP killed %2, killed %3, implicit-def $nzcv
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%4:gpr32 = COPY $wzr
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%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
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$w0 = COPY %5
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RET_ReallyLR implicit $w0
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...
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---
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name: whilegt_b16_s32
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr32 }
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- { id: 1, class: gpr32 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: ppr }
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- { id: 5, class: ppr }
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- { id: 6, class: gpr32 }
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- { id: 7, class: gpr32 }
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liveins:
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- { reg: '$w0', virtual-reg: '%0' }
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- { reg: '$w1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $w0, $w1
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; CHECK-LABEL: name: whilegt_b16_s32
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; CHECK-NOT: PTEST
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%1:gpr32 = COPY $w1
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%0:gpr32 = COPY $w0
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%2:ppr = PTRUE_H 31
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%4:ppr = WHILEGT_PWW_H %0, %1, implicit-def dead $nzcv
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PTEST_PP %2, %4, implicit-def $nzcv
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%6:gpr32 = COPY $wzr
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%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
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$w0 = COPY %7
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RET_ReallyLR implicit $w0
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...
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---
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name: whilegt_b16_s64
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64 }
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- { id: 1, class: gpr64 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: ppr }
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- { id: 5, class: ppr }
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- { id: 6, class: gpr32 }
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- { id: 7, class: gpr32 }
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liveins:
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- { reg: '$x0', virtual-reg: '%0' }
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- { reg: '$x1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; CHECK-LABEL: name: whilegt_b16_s64
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; CHECK-NOT: PTEST
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%1:gpr64 = COPY $x1
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%0:gpr64 = COPY $x0
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%2:ppr = PTRUE_H 31
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%4:ppr = WHILEGT_PXX_H %0, %1, implicit-def dead $nzcv
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PTEST_PP %2, %4, implicit-def $nzcv
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%6:gpr32 = COPY $wzr
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%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
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$w0 = COPY %7
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RET_ReallyLR implicit $w0
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...
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---
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name: whilegt_b32_s32
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr32 }
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- { id: 1, class: gpr32 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: ppr }
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- { id: 5, class: ppr }
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- { id: 6, class: gpr32 }
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- { id: 7, class: gpr32 }
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liveins:
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- { reg: '$w0', virtual-reg: '%0' }
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- { reg: '$w1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $w0, $w1
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; CHECK-LABEL: name: whilegt_b32_s32
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; CHECK-NOT: PTEST
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%1:gpr32 = COPY $w1
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%0:gpr32 = COPY $w0
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%2:ppr = PTRUE_S 31
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%4:ppr = WHILEGT_PWW_S %0, %1, implicit-def dead $nzcv
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PTEST_PP %2, %4, implicit-def $nzcv
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%6:gpr32 = COPY $wzr
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%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
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$w0 = COPY %7
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RET_ReallyLR implicit $w0
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...
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---
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name: whilegt_b32_s64
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64 }
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- { id: 1, class: gpr64 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: ppr }
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- { id: 5, class: ppr }
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- { id: 6, class: gpr32 }
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- { id: 7, class: gpr32 }
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liveins:
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- { reg: '$x0', virtual-reg: '%0' }
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- { reg: '$x1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; CHECK-LABEL: name: whilegt_b32_s64
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; CHECK-NOT: PTEST
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%1:gpr64 = COPY $x1
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%0:gpr64 = COPY $x0
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%2:ppr = PTRUE_S 31
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%4:ppr = WHILEGT_PXX_S %0, %1, implicit-def dead $nzcv
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PTEST_PP %2, %4, implicit-def $nzcv
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%6:gpr32 = COPY $wzr
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%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
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$w0 = COPY %7
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RET_ReallyLR implicit $w0
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...
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---
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name: whilegt_b64_s32
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr32 }
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- { id: 1, class: gpr32 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: ppr }
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- { id: 5, class: ppr }
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- { id: 6, class: gpr32 }
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- { id: 7, class: gpr32 }
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liveins:
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- { reg: '$w0', virtual-reg: '%0' }
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- { reg: '$w1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $w0, $w1
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; CHECK-LABEL: name: whilegt_b64_s32
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; CHECK-NOT: PTEST
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%1:gpr32 = COPY $w1
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%0:gpr32 = COPY $w0
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%2:ppr = PTRUE_D 31
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%4:ppr = WHILEGT_PWW_D %0, %1, implicit-def dead $nzcv
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PTEST_PP %2, %4, implicit-def $nzcv
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%6:gpr32 = COPY $wzr
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%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
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$w0 = COPY %7
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RET_ReallyLR implicit $w0
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...
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---
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name: whilegt_b64_s64
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64 }
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- { id: 1, class: gpr64 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: ppr }
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- { id: 5, class: ppr }
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- { id: 6, class: gpr32 }
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- { id: 7, class: gpr32 }
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liveins:
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- { reg: '$x0', virtual-reg: '%0' }
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- { reg: '$x1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; CHECK-LABEL: name: whilegt_b64_s64
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; CHECK-NOT: PTEST
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%1:gpr64 = COPY $x1
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%0:gpr64 = COPY $x0
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%2:ppr = PTRUE_D 31
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%4:ppr = WHILEGT_PXX_D %0, %1, implicit-def dead $nzcv
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PTEST_PP %2, %4, implicit-def $nzcv
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%6:gpr32 = COPY $wzr
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%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
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$w0 = COPY %7
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RET_ReallyLR implicit $w0
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...
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---
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name: whilegt_b16_s64_keep_ptest_not_all_active
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64 }
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- { id: 1, class: gpr64 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: gpr32 }
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- { id: 5, class: gpr32 }
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liveins:
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- { reg: '$x0', virtual-reg: '%0' }
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- { reg: '$x1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; PTEST is not redundant when it's Pg operand is not an all active predicate
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; of element size matching the WHILEGT, which is the implicitly predicate
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; used by WHILE when calculating the condition codes.
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;
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; CHECK-LABEL: name: whilegt_b16_s64_keep_ptest_not_all_active
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; CHECK: %3:ppr = WHILEGT_PXX_H %0, %1, implicit-def dead $nzcv
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; CHECK-NEXT: PTEST_PP killed %2, killed %3, implicit-def $nzcv
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; CHECK-NEXT: %4:gpr32 = COPY $wzr
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; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
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%1:gpr64 = COPY $x1
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%0:gpr64 = COPY $x0
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%2:ppr = PTRUE_H 1
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%3:ppr = WHILEGT_PXX_H %0, %1, implicit-def dead $nzcv
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PTEST_PP killed %2, killed %3, implicit-def $nzcv
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%4:gpr32 = COPY $wzr
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%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
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$w0 = COPY %5
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RET_ReallyLR implicit $w0
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...
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---
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name: whilegt_b16_s64_keep_ptest_of_bytes
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64 }
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- { id: 1, class: gpr64 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: gpr32 }
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- { id: 5, class: gpr32 }
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liveins:
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- { reg: '$x0', virtual-reg: '%0' }
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- { reg: '$x1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; PTEST is not redundant when it's Pg operand is not an all active predicate
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; of element size matching the WHILEGT, which is the implicitly predicate
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; used by WHILE when calculating the condition codes.
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;
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; CHECK-LABEL: name: whilegt_b16_s64_keep_ptest_of_bytes
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; CHECK: %3:ppr = WHILEGT_PXX_H %0, %1, implicit-def dead $nzcv
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; CHECK-NEXT: PTEST_PP killed %2, killed %3, implicit-def $nzcv
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; CHECK-NEXT: %4:gpr32 = COPY $wzr
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; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
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%1:gpr64 = COPY $x1
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%0:gpr64 = COPY $x0
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%2:ppr = PTRUE_B 31
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%3:ppr = WHILEGT_PXX_H %0, %1, implicit-def dead $nzcv
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PTEST_PP killed %2, killed %3, implicit-def $nzcv
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%4:gpr32 = COPY $wzr
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%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
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$w0 = COPY %5
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RET_ReallyLR implicit $w0
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...
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---
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name: whilegt_b16_s64_keep_ptest_of_words
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64 }
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- { id: 1, class: gpr64 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: gpr32 }
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- { id: 5, class: gpr32 }
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liveins:
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- { reg: '$x0', virtual-reg: '%0' }
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- { reg: '$x1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; PTEST is not redundant when it's Pg operand is not an all active predicate
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; of element size matching the WHILEGT, which is the implicitly predicate
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; used by WHILE when calculating the condition codes.
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;
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; CHECK-LABEL: name: whilegt_b16_s64_keep_ptest_of_words
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; CHECK: %3:ppr = WHILEGT_PXX_H %0, %1, implicit-def dead $nzcv
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; CHECK-NEXT: PTEST_PP killed %2, killed %3, implicit-def $nzcv
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; CHECK-NEXT: %4:gpr32 = COPY $wzr
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; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
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%1:gpr64 = COPY $x1
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%0:gpr64 = COPY $x0
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%2:ppr = PTRUE_S 31
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%3:ppr = WHILEGT_PXX_H %0, %1, implicit-def dead $nzcv
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PTEST_PP killed %2, killed %3, implicit-def $nzcv
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%4:gpr32 = COPY $wzr
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%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
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$w0 = COPY %5
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RET_ReallyLR implicit $w0
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...
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---
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name: whilegt_b16_s64_keep_ptest_of_doublewords
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64 }
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- { id: 1, class: gpr64 }
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- { id: 2, class: ppr }
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- { id: 3, class: ppr }
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- { id: 4, class: gpr32 }
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- { id: 5, class: gpr32 }
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liveins:
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- { reg: '$x0', virtual-reg: '%0' }
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- { reg: '$x1', virtual-reg: '%1' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; PTEST is not redundant when it's Pg operand is not an all active predicate
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; of element size matching the WHILEGT, which is the implicitly predicate
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; used by WHILE when calculating the condition codes.
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;
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; CHECK-LABEL: name: whilegt_b16_s64_keep_ptest_of_doublewords
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; CHECK: %3:ppr = WHILEGT_PXX_H %0, %1, implicit-def dead $nzcv
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; CHECK-NEXT: PTEST_PP killed %2, killed %3, implicit-def $nzcv
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; CHECK-NEXT: %4:gpr32 = COPY $wzr
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; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
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%1:gpr64 = COPY $x1
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%0:gpr64 = COPY $x0
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%2:ppr = PTRUE_D 31
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%3:ppr = WHILEGT_PXX_H %0, %1, implicit-def dead $nzcv
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PTEST_PP killed %2, killed %3, implicit-def $nzcv
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%4:gpr32 = COPY $wzr
|
|
%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
|
|
$w0 = COPY %5
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|
|
---
|
|
name: whilegt_b8_s32_ptest_with_matching_operands
|
|
alignment: 2
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gpr32 }
|
|
- { id: 1, class: gpr32 }
|
|
- { id: 2, class: ppr }
|
|
- { id: 3, class: gpr32 }
|
|
- { id: 4, class: gpr32 }
|
|
liveins:
|
|
- { reg: '$w0', virtual-reg: '%0' }
|
|
- { reg: '$w1', virtual-reg: '%1' }
|
|
frameInfo:
|
|
maxCallFrameSize: 0
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $w0, $w1
|
|
|
|
; CHECK-LABEL: name: whilegt_b8_s32_ptest_with_matching_operands
|
|
; CHECK-NOT: PTEST
|
|
%1:gpr32 = COPY $w1
|
|
%0:gpr32 = COPY $w0
|
|
%2:ppr = WHILEGT_PWW_B %0, %1, implicit-def dead $nzcv
|
|
PTEST_PP %2, killed %2, implicit-def $nzcv
|
|
%3:gpr32 = COPY $wzr
|
|
%4:gpr32 = CSINCWr %3, $wzr, 0, implicit $nzcv
|
|
$w0 = COPY %4
|
|
RET_ReallyLR implicit $w0
|
|
|
|
...
|