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da5a339f73
The Windows on ARM target uses custom division for normal division as the backend needs to insert division-by-zero checks. However, it is designed to only handle non-vectorized division. ARM has custom lowering for vectorized division as that can avoid loading registers with the values and invoke a division routine for each one, preferring to lower using NEON instructions. Fall back to the custom lowering for the NEON instructions if we encounter a vectorized division. Resolves PR31778! llvm-svn: 293259
59 lines
1.5 KiB
LLVM
59 lines
1.5 KiB
LLVM
; RUN: llc -mtriple arm-eabi -mattr=+neon -disable-post-ra -pre-RA-sched source %s -o - | FileCheck %s
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; RUN: llc -mtriple thumbv7-windows-itanium -mattr=+neon -disable-post-ra -pre-RA-sched source %s -o - | FileCheck %s
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define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = sdiv <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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; CHECK-LABEL: sdivi8:
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; CHECK: vrecpe.f32
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; CHECK: vmovn.i32
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; CHECK: vrecpe.f32
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; CHECK: vmovn.i32
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; CHECK: vmovn.i16
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define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = udiv <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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; CHECK-LABEL: udivi8:
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; CHECK: vrecpe.f32
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; CHECK: vrecps.f32
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; CHECK: vmovn.i32
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; CHECK: vrecpe.f32
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; CHECK: vrecps.f32
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; CHECK: vmovn.i32
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; CHECK: vqmovun.s16
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define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = sdiv <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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; CHECK-LABEL: sdivi16:
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; CHECK: vrecpe.f32
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; CHECK: vrecps.f32
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; CHECK: vmovn.i32
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define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = udiv <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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; CHECK-LABEL: udivi16:
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; CHECK: vrecpe.f32
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; CHECK: vrecps.f32
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; CHECK: vrecps.f32
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; CHECK: vmovn.i32
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