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https://github.com/RPCS3/llvm-mirror.git
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6f6fdb453a
Second half of PR40800, this patch adds DAG undef handling to fcmp instructions to match the behavior in llvm::ConstantFoldCompareInstruction, this permits constant folding of vector comparisons where some elements had been reduced to UNDEF (by SimplifyDemandedVectorElts etc.). This involves a lot of tweaking to reduced tests as bugpoint loves to reduce fcmp arguments to undef........ Differential Revision: https://reviews.llvm.org/D60006 llvm-svn: 357765
305 lines
9.9 KiB
LLVM
305 lines
9.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s
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define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vcges8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vcge.s8 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = icmp sge <8 x i8> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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; CHECK-LABEL: vcges16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vcge.s16 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = icmp sge <4 x i16> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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; CHECK-LABEL: vcges32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vcge.s32 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%tmp3 = icmp sge <2 x i32> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vcgeu8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vcge.u8 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = icmp uge <8 x i8> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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; CHECK-LABEL: vcgeu16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vcge.u16 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = icmp uge <4 x i16> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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; CHECK-LABEL: vcgeu32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vcge.u32 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%tmp3 = icmp uge <2 x i32> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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; CHECK-LABEL: vcgef32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vcge.f32 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = fcmp oge <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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; CHECK-LABEL: vcgeQs8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vcge.s8 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = icmp sge <16 x i8> %tmp1, %tmp2
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%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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; CHECK-LABEL: vcgeQs16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vcge.s16 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = icmp sge <8 x i16> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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; CHECK-LABEL: vcgeQs32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vcge.s32 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = load <4 x i32>, <4 x i32>* %B
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%tmp3 = icmp sge <4 x i32> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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; CHECK-LABEL: vcgeQu8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vcge.u8 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = icmp uge <16 x i8> %tmp1, %tmp2
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%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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; CHECK-LABEL: vcgeQu16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vcge.u16 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = icmp uge <8 x i16> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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; CHECK-LABEL: vcgeQu32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vcge.u32 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = load <4 x i32>, <4 x i32>* %B
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%tmp3 = icmp uge <4 x i32> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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; CHECK-LABEL: vcgeQf32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vcge.f32 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = fcmp oge <4 x float> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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; CHECK-LABEL: vacgef32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vacge.f32 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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; CHECK-LABEL: vacgeQf32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vacge.f32 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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ret <4 x i32> %tmp3
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}
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declare <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
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; CHECK-LABEL: vcgei8Z:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vcge.s8 d16, d16, #0
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp3 = icmp sge <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
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; CHECK-LABEL: vclei8Z:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vcle.s8 d16, d16, #0
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp3 = icmp sle <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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; Radar 8782191
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; Floating-point comparisons against zero produce results with integer
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; elements, not floating-point elements.
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define void @test_vclez_fp(<4 x float>* %A) nounwind optsize {
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; CHECK-LABEL: test_vclez_fp:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vcle.f32 q8, q8, #0
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; CHECK-NEXT: vmovn.i32 d16, q8
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; CHECK-NEXT: vmov.i8 d17, #0x1
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; CHECK-NEXT: vuzp.8 d16, d18
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; CHECK-NEXT: vadd.i8 d16, d16, d17
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; CHECK-NEXT: vst1.8 {d16}, [r0]
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entry:
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%ld = load <4 x float>, <4 x float>* %A
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%0 = fcmp ole <4 x float> %ld, zeroinitializer
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%1 = sext <4 x i1> %0 to <4 x i16>
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%2 = add <4 x i16> %1, zeroinitializer
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%3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%4 = add <8 x i16> %3, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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%5 = trunc <8 x i16> %4 to <8 x i8>
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tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* undef, <8 x i8> %5, i32 1)
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unreachable
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}
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declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind
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