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https://github.com/RPCS3/llvm-mirror.git
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c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
40 lines
1.7 KiB
LLVM
40 lines
1.7 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Test that we compile the HVX dual output intrinsics.
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; CHECK-LABEL: f0:
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; CHECK: v{{[0-9]+}}.w = vadd(v{{[0-9]+}}.w,v{{[0-9]+}}.w,q{{[0-3]}}):carry
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define inreg <16 x i32> @f0(<16 x i32> %a0, <16 x i32> %a1, i8* nocapture readonly %a2) #0 {
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b0:
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%v0 = bitcast i8* %a2 to <16 x i32>*
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%v1 = load <16 x i32>, <16 x i32>* %v0, align 64
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%v2 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v1, i32 -1)
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%v3 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v2)
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%v4 = extractvalue { <16 x i32>, <64 x i1> } %v3, 0
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ret <16 x i32> %v4
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}
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; CHECK-LABEL: f1:
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; CHECK: v{{[0-9]+}}.w = vsub(v{{[0-9]+}}.w,v{{[0-9]+}}.w,q{{[0-3]}}):carry
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define inreg <16 x i32> @f1(<16 x i32> %a0, <16 x i32> %a1, i8* nocapture readonly %a2) #0 {
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b0:
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%v0 = bitcast i8* %a2 to <16 x i32>*
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%v1 = load <16 x i32>, <16 x i32>* %v0, align 64
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%v2 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v1, i32 -1)
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%v3 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v2)
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%v4 = extractvalue { <16 x i32>, <64 x i1> } %v3, 0
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ret <16 x i32> %v4
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}
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; Function Attrs: nounwind readnone
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declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32>, <16 x i32>, <64 x i1>) #1
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; Function Attrs: nounwind readnone
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declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32>, <16 x i32>, <64 x i1>) #1
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; Function Attrs: nounwind readnone
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declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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