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deb679e8ad
Implementation for RISC-V Zbr extension intrinsic.
Header files are included in separate patch in case the name needs to be changed
RV32 / 64:
crc32b
crc32h
crc32w
crc32cb
crc32ch
crc32cw
RV64 Only:
crc32d
crc32cd
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D99009
92 lines
2.2 KiB
LLVM
92 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64ZBR
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declare i64 @llvm.riscv.crc32.b.i64(i64)
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define i64 @crc32b(i64 %a) nounwind {
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; RV64ZBR-LABEL: crc32b:
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; RV64ZBR: # %bb.0:
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; RV64ZBR-NEXT: crc32.b a0, a0
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; RV64ZBR-NEXT: ret
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%tmp = call i64 @llvm.riscv.crc32.b.i64(i64 %a)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.crc32.h.i64(i64)
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define i64 @crc32h(i64 %a) nounwind {
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; RV64ZBR-LABEL: crc32h:
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; RV64ZBR: # %bb.0:
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; RV64ZBR-NEXT: crc32.h a0, a0
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; RV64ZBR-NEXT: ret
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%tmp = call i64 @llvm.riscv.crc32.h.i64(i64 %a)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.crc32.w.i64(i64)
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define i64 @crc32w(i64 %a) nounwind {
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; RV64ZBR-LABEL: crc32w:
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; RV64ZBR: # %bb.0:
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; RV64ZBR-NEXT: crc32.w a0, a0
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; RV64ZBR-NEXT: ret
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%tmp = call i64 @llvm.riscv.crc32.w.i64(i64 %a)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.crc32c.b.i64(i64)
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define i64 @crc32cb(i64 %a) nounwind {
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; RV64ZBR-LABEL: crc32cb:
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; RV64ZBR: # %bb.0:
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; RV64ZBR-NEXT: crc32c.b a0, a0
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; RV64ZBR-NEXT: ret
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%tmp = call i64 @llvm.riscv.crc32c.b.i64(i64 %a)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.crc32c.h.i64(i64)
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define i64 @crc32ch(i64 %a) nounwind {
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; RV64ZBR-LABEL: crc32ch:
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; RV64ZBR: # %bb.0:
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; RV64ZBR-NEXT: crc32c.h a0, a0
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; RV64ZBR-NEXT: ret
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%tmp = call i64 @llvm.riscv.crc32c.h.i64(i64 %a)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.crc32c.w.i64(i64)
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define i64 @crc32cw(i64 %a) nounwind {
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; RV64ZBR-LABEL: crc32cw:
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; RV64ZBR: # %bb.0:
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; RV64ZBR-NEXT: crc32c.w a0, a0
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; RV64ZBR-NEXT: ret
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%tmp = call i64 @llvm.riscv.crc32c.w.i64(i64 %a)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.crc32.d.i64(i64)
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define i64 @crc32d(i64 %a) nounwind {
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; RV64ZBR-LABEL: crc32d:
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; RV64ZBR: # %bb.0:
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; RV64ZBR-NEXT: crc32.d a0, a0
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; RV64ZBR-NEXT: ret
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%tmp = call i64 @llvm.riscv.crc32.d.i64(i64 %a)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.crc32c.d.i64(i64)
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define i64 @crc32cd(i64 %a) nounwind {
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; RV64ZBR-LABEL: crc32cd:
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; RV64ZBR: # %bb.0:
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; RV64ZBR-NEXT: crc32c.d a0, a0
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; RV64ZBR-NEXT: ret
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%tmp = call i64 @llvm.riscv.crc32c.d.i64(i64 %a)
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ret i64 %tmp
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}
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