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e7104f6f7b
* vreg <-> vreg joining now works, enable it unconditionally when joining is enabled (which is the default). * Fix a serious pessimization of spill code where we were saying that a spilled DEF operand was live into the subsequent instruction. This allows for substantially better code when spilling starts to happen. llvm-svn: 14993 |
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.. | ||
InstrSched | ||
ModuloScheduling | ||
SelectionDAG | ||
IntrinsicLowering.cpp | ||
LiveIntervals.cpp | ||
LiveIntervals.h | ||
LiveVariables.cpp | ||
MachineBasicBlock.cpp | ||
MachineCodeEmitter.cpp | ||
MachineCodeForInstruction.cpp | ||
MachineFunction.cpp | ||
MachineInstr.cpp | ||
MachineInstrAnnot.cpp | ||
Makefile | ||
Passes.cpp | ||
PHIElimination.cpp | ||
PhysRegTracker.h | ||
PrologEpilogInserter.cpp | ||
RegAllocLinearScan.cpp | ||
RegAllocLocal.cpp | ||
RegAllocSimple.cpp | ||
TwoAddressInstructionPass.cpp | ||
UnreachableBlockElim.cpp | ||
VirtRegMap.cpp | ||
VirtRegMap.h |