Silviu Baranga e74bc9b8dc Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation. ... llvm-svn: 173437		2013-01-25 10:39:49 +00:00
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ARM	Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation.	2013-01-25 10:39:49 +00:00
CPP
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
Hexagon	Add indexed load/store instructions for offset validation check.	2013-01-17 18:42:37 +00:00
MBlaze
Mips	[mips] Set flag neverHasSideEffects flag on some of the floating point instructions.	2013-01-25 00:20:39 +00:00
MSP430
NVPTX
PowerPC	Restore reverted test case, this time with REQUIRES: asserts	2013-01-17 19:46:51 +00:00
R600	DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes	2013-01-02 22:13:01 +00:00
SI
SPARC
Thumb
Thumb2	Remove some register allocation order dependencies.	2013-01-19 00:03:32 +00:00
X86	MIsched: Improve the interface to SchedDFS analysis (subtrees).	2013-01-25 06:33:57 +00:00
XCore