Simon Pilgrim ec0f8ea81f [X86][AVX] Add shuffle masking support for EltsFromConsecutiveLoads ... Add support for the case where we have a consecutive load (which must include the first + last elements) with a mixture of undef/zero elements. We load the vector and then apply a shuffle to clear the zero'd elements. Differential Revision: http://reviews.llvm.org/D17297 llvm-svn: 261490		2016-02-21 19:15:48 +00:00
..
AArch64	[AArch64][ShrinkWrap] Fix bug in prolog clobbering live reg when shrink wrapping.	2016-02-19 18:27:32 +00:00
AMDGPU	AMDGPU/SI: Use v_readfirstlane to legalize SMRD with VGPR base pointer	2016-02-20 00:37:25 +00:00
ARM	[RegAllocFast] Properly track the physical register definitions on calls.	2016-02-20 00:32:29 +00:00
BPF
CPP
Generic	Revert r261070, it caused PR26652 / PR26653.	2016-02-17 18:47:29 +00:00
Hexagon	[Hexagon] Implement TLS support	2016-02-18 15:42:57 +00:00
Inputs
Mips	[MC][ELF] Handle MIPS specific .sdata and .sbss directives	2016-02-11 06:45:54 +00:00
MIR	When printing MIR, output to errs() rather than outs().	2016-02-19 00:18:46 +00:00
MSP430
NVPTX	[NVPTX] Test that MachineSink won't sink across llvm.cuda.syncthreads.	2016-02-17 17:46:52 +00:00
PowerPC	When printing MIR, output to errs() rather than outs().	2016-02-19 00:18:46 +00:00
SPARC
SystemZ	[SystemZ] Fix ABI for i128 argument and return types	2016-02-19 14:10:21 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Support physical registers in the rewrite-to-discard optimization.	2016-02-21 03:27:22 +00:00
WinEH	[WinEH] Optimize WinEH state stores	2016-02-17 18:37:11 +00:00
X86	[X86][AVX] Add shuffle masking support for EltsFromConsecutiveLoads	2016-02-21 19:15:48 +00:00
XCore