Simon Pilgrim ecd973d988 [SelectionDAG] BITREVERSE vector legalization of bit operations ... Vector bit operations are typically promoted instead of having custom lowering. This patch changes the isOperationLegalOrCustom tests for vector AND/OR operations to use isOperationLegalOrPromote instead, allowing the SSE implementations to stay on the simd unit. Differential Revision: http://reviews.llvm.org/D19805 llvm-svn: 268504		2016-05-04 15:01:13 +00:00
..
AArch64	Fix uppercase typo	2016-05-03 05:21:53 +00:00
AMDGPU	AMDGPU: Custom lower v2i32 loads and stores	2016-05-02 20:13:51 +00:00
ARM	[ARM] Set correct successors in CMPXCHG pseudo expansion.	2016-04-27 20:32:54 +00:00
BPF
CPP
Generic
Hexagon	[Hexagon] Optimize addressing modes for load/store	2016-04-29 15:49:13 +00:00
Inputs
Lanai
Mips	[mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions	2016-05-04 12:02:12 +00:00
MIR	ARM: fix handling of SUB immediates in peephole opt.	2016-05-02 18:30:08 +00:00
MSP430
NVPTX	[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection	2016-05-02 18:12:02 +00:00
PowerPC	[MBP] Use Function::optForSize() instead of checking OptimizeForSize directly.	2016-04-29 22:01:10 +00:00
SPARC	[Sparc] Allow taking of function address into a register.	2016-05-04 12:11:05 +00:00
SystemZ	[SystemZ] Temporarily disable codegen test int-add-12.ll.	2016-05-02 10:42:47 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Rename memory_size intrinsic to current_memory	2016-05-02 17:25:22 +00:00
WinEH
X86	[SelectionDAG] BITREVERSE vector legalization of bit operations	2016-05-04 15:01:13 +00:00
XCore