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e0dc000a0d
We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
181 lines
6.9 KiB
C++
181 lines
6.9 KiB
C++
//===-- llvm/lib/Target/AArch64/AArch64CallLowering.cpp - Call lowering ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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///
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//===----------------------------------------------------------------------===//
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#include "AArch64CallLowering.h"
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#include "AArch64ISelLowering.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "This shouldn't be built without GISel"
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#endif
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AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
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: CallLowering(&TLI) {
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}
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bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, unsigned VReg) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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MachineInstrBuilder MIB = MIRBuilder.buildInstr(AArch64::RET_ReallyLR);
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assert(MIB.getInstr() && "Unable to build a return instruction?!");
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assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
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if (VReg) {
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MIRBuilder.setInstr(*MIB.getInstr(), /* Before */ true);
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
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handleAssignments(MIRBuilder, AssignFn, Val->getType(), VReg,
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[&](MachineIRBuilder &MIRBuilder, Type *Ty,
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unsigned ValReg, unsigned PhysReg) {
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MIRBuilder.buildCopy(PhysReg, ValReg);
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MIB.addUse(PhysReg, RegState::Implicit);
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});
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}
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return true;
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}
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bool AArch64CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
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CCAssignFn *AssignFn,
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ArrayRef<Type *> ArgTypes,
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ArrayRef<unsigned> ArgRegs,
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AssignFnTy AssignValToReg) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
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unsigned NumArgs = ArgTypes.size();
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auto CurTy = ArgTypes.begin();
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for (unsigned i = 0; i != NumArgs; ++i, ++CurTy) {
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MVT CurVT = MVT::getVT(*CurTy);
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if (AssignFn(i, CurVT, CurVT, CCValAssign::Full, ISD::ArgFlagsTy(), CCInfo))
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return false;
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}
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assert(ArgLocs.size() == ArgTypes.size() &&
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"We have a different number of location and args?!");
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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// FIXME: Support non-register argument.
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if (!VA.isRegLoc())
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return false;
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switch (VA.getLocInfo()) {
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default:
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// Unknown loc info!
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return false;
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case CCValAssign::Full:
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break;
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case CCValAssign::BCvt:
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// We don't care about bitcast.
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break;
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case CCValAssign::AExt:
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// Existing high bits are fine for anyext (whatever they are).
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break;
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case CCValAssign::SExt:
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case CCValAssign::ZExt:
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// Zero/Sign extend the register.
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// FIXME: Not yet implemented
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return false;
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}
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// Everything checks out, tell the caller where we've decided this
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// parameter/return value should go.
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AssignValToReg(MIRBuilder, ArgTypes[i], ArgRegs[i], VA.getLocReg());
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}
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return true;
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}
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bool AArch64CallLowering::lowerFormalArguments(
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MachineIRBuilder &MIRBuilder, const Function::ArgumentListType &Args,
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ArrayRef<unsigned> VRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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SmallVector<Type *, 8> ArgTys;
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for (auto &Arg : Args)
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ArgTys.push_back(Arg.getType());
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *AssignFn =
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TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
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return handleAssignments(MIRBuilder, AssignFn, ArgTys, VRegs,
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[](MachineIRBuilder &MIRBuilder, Type *Ty,
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unsigned ValReg, unsigned PhysReg) {
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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MIRBuilder.buildCopy(ValReg, PhysReg);
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});
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}
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bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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const MachineOperand &Callee,
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ArrayRef<Type *> ResTys,
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ArrayRef<unsigned> ResRegs,
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ArrayRef<Type *> ArgTys,
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ArrayRef<unsigned> ArgRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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// Find out which ABI gets to decide where things go.
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *CallAssignFn =
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TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
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// And finally we can do the actual assignments. For a call we need to keep
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// track of the registers used because they'll be implicit uses of the BL.
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SmallVector<unsigned, 8> PhysRegs;
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handleAssignments(MIRBuilder, CallAssignFn, ArgTys, ArgRegs,
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[&](MachineIRBuilder &MIRBuilder, Type *Ty, unsigned ValReg,
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unsigned PhysReg) {
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MIRBuilder.buildCopy(PhysReg, ValReg);
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PhysRegs.push_back(PhysReg);
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});
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// Now we can build the actual call instruction.
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auto MIB = MIRBuilder.buildInstr(Callee.isReg() ? AArch64::BLR : AArch64::BL);
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MIB.addOperand(Callee);
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// Tell the call which registers are clobbered.
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auto TRI = MF.getSubtarget().getRegisterInfo();
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MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
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for (auto Reg : PhysRegs)
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MIB.addUse(Reg, RegState::Implicit);
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// Finally we can copy the returned value back into its virtual-register. In
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// symmetry with the arugments, the physical register must be an
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// implicit-define of the call instruction.
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CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
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if (!ResRegs.empty())
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handleAssignments(MIRBuilder, RetAssignFn, ResTys, ResRegs,
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[&](MachineIRBuilder &MIRBuilder, Type *Ty,
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unsigned ValReg, unsigned PhysReg) {
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MIRBuilder.buildCopy(ValReg, PhysReg);
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MIB.addDef(PhysReg, RegState::Implicit);
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});
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return true;
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}
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