Andrea Di Biagio 41bcee5bc3 [X86] Add ISel patterns to improve the selection of TZCNT and LZCNT. ... Instructions TZCNT (requires BMI1) and LZCNT (requires LZCNT), always provide the operand size as output if the input operand is zero. We can take advantage of this knowledge during instruction selection stage in order to simplify a few corner case. llvm-svn: 209159		2014-05-19 20:38:59 +00:00
..
AArch64	Revert "Implement global merge optimization for global variables."	2014-05-16 13:02:18 +00:00
ARM	SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the bswap not.	2014-05-19 13:12:38 +00:00
ARM64	[ARM64] Split tbz/tbnz into W/X register variant	2014-05-19 15:58:15 +00:00
CPP
Generic	MC: move test from Generic to COFF	2014-04-23 21:41:07 +00:00
Hexagon	reverting r209132	2014-05-19 16:22:11 +00:00
Inputs
Mips	Finish materialize for ints	2014-05-15 21:54:15 +00:00
MSP430	Mark FPB as a reserved register when needed.	2014-04-02 13:13:56 +00:00
NVPTX	Fix the test: DCE optimized away everything.	2014-04-21 17:23:12 +00:00
PowerPC	DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.	2014-05-14 21:52:46 +00:00
R600	R600/SI: Promote f32 SELECT to i32	2014-05-16 20:56:41 +00:00
SPARC	TableGen: fix operand counting for aliases	2014-05-16 09:42:04 +00:00
SystemZ	Reenable use of TBAA during CodeGen	2014-04-12 01:26:00 +00:00
Thumb	Re-enable inline memcpy expansion for Thumb1.	2014-05-16 14:24:22 +00:00
Thumb2	Fix the Load/Store optimization pass to work with Thumb1.	2014-05-16 14:14:30 +00:00
X86	[X86] Add ISel patterns to improve the selection of TZCNT and LZCNT.	2014-05-19 20:38:59 +00:00
XCore	Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"	2014-04-21 17:57:07 +00:00