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On modern Intel processors hardware SQRT in many cases is faster than RSQRT followed by Newton-Raphson refinement. The patch introduces a simple heuristic to choose between hardware SQRT instruction and Newton-Raphson software estimation. The patch treats scalars and vectors differently. The heuristic is that for scalars the compiler should optimize for latency while for vectors it should optimize for throughput. It is based on the assumption that throughput bound code is likely to be vectorized. Basically, the patch disables scalar NR for big cores and disables NR completely for Skylake. Firstly, scalar SQRT has shorter latency than NR code in big cores. Secondly, vector SQRT has been greatly improved in Skylake and has better throughput compared to NR. Differential Revision: https://reviews.llvm.org/D21379 llvm-svn: 277725 |
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| .. | ||
| CMakeLists.txt | ||
| DAGCombiner.cpp | ||
| FastISel.cpp | ||
| FunctionLoweringInfo.cpp | ||
| InstrEmitter.cpp | ||
| InstrEmitter.h | ||
| LegalizeDAG.cpp | ||
| LegalizeFloatTypes.cpp | ||
| LegalizeIntegerTypes.cpp | ||
| LegalizeTypes.cpp | ||
| LegalizeTypes.h | ||
| LegalizeTypesGeneric.cpp | ||
| LegalizeVectorOps.cpp | ||
| LegalizeVectorTypes.cpp | ||
| LLVMBuild.txt | ||
| ResourcePriorityQueue.cpp | ||
| ScheduleDAGFast.cpp | ||
| ScheduleDAGRRList.cpp | ||
| ScheduleDAGSDNodes.cpp | ||
| ScheduleDAGSDNodes.h | ||
| ScheduleDAGVLIW.cpp | ||
| SDNodeDbgValue.h | ||
| SelectionDAG.cpp | ||
| SelectionDAGBuilder.cpp | ||
| SelectionDAGBuilder.h | ||
| SelectionDAGDumper.cpp | ||
| SelectionDAGISel.cpp | ||
| SelectionDAGPrinter.cpp | ||
| SelectionDAGTargetInfo.cpp | ||
| StatepointLowering.cpp | ||
| StatepointLowering.h | ||
| TargetLowering.cpp | ||