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d49cb60862
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
74 lines
2.0 KiB
YAML
74 lines
2.0 KiB
YAML
# RUN: llc -mtriple=aarch64-none-linux-android -run-pass aarch64-ldst-opt -o - %s | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-linux-android"
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define void @f(i64* nocapture %x) "target-features"="+mte" {
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entry:
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store i64 1, i64* %x, align 8
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%0 = tail call i8* @llvm.aarch64.irg(i8* null, i64 0)
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%1 = tail call i8* @llvm.aarch64.irg.sp(i64 0)
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%arrayidx1 = getelementptr inbounds i64, i64* %x, i64 1
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store i64 1, i64* %arrayidx1, align 8
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ret void
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}
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declare i8* @llvm.aarch64.irg(i8*, i64) nounwind
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declare i8* @llvm.aarch64.irg.sp(i64) nounwind
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...
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---
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name: f
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$x0', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x0
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$x8 = ORRXrs $xzr, $xzr, 0
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$w9 = MOVZWi 1, 0, implicit-def $x9
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; Check that stores are merged across IRG.
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; CHECK: STPXi renamable $x9, renamable $x9, renamable $x0, 0
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STRXui renamable $x9, renamable $x0, 0 :: (store 8 into %ir.x)
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dead renamable $x10 = IRG renamable $x8, $xzr
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dead renamable $x8 = IRG $sp, $xzr
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STRXui killed renamable $x9, killed renamable $x0, 1 :: (store 8 into %ir.arrayidx1)
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RET undef $lr
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...
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