Petar Avramovic 14d56a77f5 Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect ... Recommit bf5a5826504754788a8f1e3fec7a7dc95cda5782. Depends on 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which was reverted. RegBankSelect creates zext and trunc when it selects banks for uniform i1. Add zext_trunc_fold from generic combiner to post RegBankSelect combiner. Differential Revision: https://reviews.llvm.org/D95432		2021-03-05 11:05:37 +01:00
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AArch64	[AArch64][GlobalISel][RegBankSelect] Improve rbs of G_BUILD_VECTOR when fed by fp values.	2021-03-04 15:09:05 -08:00
AMDGPU	Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect	2021-03-05 11:05:37 +01:00
ARC
ARM	[mir] Fix confusing MIR when MMO's value is nullptr but offset is non-zero	2021-03-04 10:34:30 -08:00
AVR	[AVR] Fix lifeness issues in the AVR backend	2021-03-04 14:04:39 +01:00
BPF	BPF: permit type modifiers for __builtin_btf_type_id() relocation	2021-03-04 16:27:23 -08:00
Generic
Hexagon
Inputs
Lanai
Mips
MIR	[mir] Fix confusing MIR when MMO's value is nullptr but offset is non-zero	2021-03-04 10:34:30 -08:00
MSP430
NVPTX
PowerPC	[mir] Fix confusing MIR when MMO's value is nullptr but offset is non-zero	2021-03-04 10:34:30 -08:00
RISCV	[RISCV] Fix crash when inserting large fixed-length subvectors	2021-03-04 09:27:16 +00:00
SPARC
SystemZ	[SystemZ] Reimplement the i8/i16 compare-and-swap logic.	2021-03-03 14:04:32 -06:00
Thumb
Thumb2	[ARM] KnownBits for CSINC/CSNEG/CSINV	2021-03-04 08:40:20 +00:00
VE	[test] Fix CodeGen/VE/Scalar tests	2021-03-02 15:30:44 -08:00
WebAssembly	[WebAssembly] Fix ExceptionInfo grouping again	2021-03-04 15:05:13 -08:00
WinCFGuard
WinEH
X86	[X86] Pass to transform amx intrinsics to scalar operation.	2021-03-05 16:02:02 +08:00
XCore