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I have added a new file: llvm/test/CodeGen/AArch64/README that describes what to do in the event one of the SVE codegen tests fails the warnings check. In addition, I've added comments to all the relevant SVE tests pointing users at the README file. Differential Revision: https://reviews.llvm.org/D83467
176 lines
4.1 KiB
LLVM
176 lines
4.1 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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;
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; CNTB
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;
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define i64 @cntb() {
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; CHECK-LABEL: cntb:
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; CHECK: cntb x0, vl2
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.cntb(i32 2)
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ret i64 %out
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}
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define i64 @cntb_mul3() {
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; CHECK-LABEL: cntb_mul3:
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; CHECK: cntb x0, vl6, mul #3
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntb(i32 6)
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%out = mul i64 %cnt, 3
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ret i64 %out
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}
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define i64 @cntb_mul4() {
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; CHECK-LABEL: cntb_mul4:
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; CHECK: cntb x0, vl8, mul #4
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntb(i32 8)
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%out = mul i64 %cnt, 4
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ret i64 %out
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}
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;
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; CNTH
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;
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define i64 @cnth() {
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; CHECK-LABEL: cnth:
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; CHECK: cnth x0, vl3
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.cnth(i32 3)
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ret i64 %out
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}
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define i64 @cnth_mul5() {
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; CHECK-LABEL: cnth_mul5:
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; CHECK: cnth x0, vl7, mul #5
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cnth(i32 7)
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%out = mul i64 %cnt, 5
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ret i64 %out
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}
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define i64 @cnth_mul8() {
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; CHECK-LABEL: cnth_mul8:
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; CHECK: cnth x0, vl5, mul #8
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cnth(i32 5)
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%out = mul i64 %cnt, 8
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ret i64 %out
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}
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;
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; CNTW
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;
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define i64 @cntw() {
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; CHECK-LABEL: cntw:
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; CHECK: cntw x0, vl4
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.cntw(i32 4)
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ret i64 %out
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}
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define i64 @cntw_mul11() {
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; CHECK-LABEL: cntw_mul11:
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; CHECK: cntw x0, vl8, mul #11
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntw(i32 8)
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%out = mul i64 %cnt, 11
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ret i64 %out
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}
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define i64 @cntw_mul2() {
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; CHECK-LABEL: cntw_mul2:
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; CHECK: cntw x0, vl6, mul #2
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntw(i32 6)
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%out = mul i64 %cnt, 2
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ret i64 %out
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}
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;
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; CNTD
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;
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define i64 @cntd() {
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; CHECK-LABEL: cntd:
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; CHECK: cntd x0, vl5
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.cntd(i32 5)
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ret i64 %out
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}
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define i64 @cntd_mul15() {
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; CHECK-LABEL: cntd_mul15:
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; CHECK: cntd x0, vl16, mul #15
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntd(i32 9)
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%out = mul i64 %cnt, 15
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ret i64 %out
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}
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define i64 @cntd_mul16() {
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; CHECK-LABEL: cntd_mul16:
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; CHECK: cntd x0, vl32, mul #16
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntd(i32 10)
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%out = mul i64 %cnt, 16
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ret i64 %out
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}
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;
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; CNTP
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;
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define i64 @cntp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; CHECK-LABEL: cntp_b8:
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; CHECK: cntp x0, p0, p1.b
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %pg,
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<vscale x 16 x i1> %a)
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ret i64 %out
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}
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define i64 @cntp_b16(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a) {
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; CHECK-LABEL: cntp_b16:
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; CHECK: cntp x0, p0, p1.h
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %pg,
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<vscale x 8 x i1> %a)
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ret i64 %out
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}
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define i64 @cntp_b32(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a) {
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; CHECK-LABEL: cntp_b32:
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; CHECK: cntp x0, p0, p1.s
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %pg,
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<vscale x 4 x i1> %a)
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ret i64 %out
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}
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define i64 @cntp_b64(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a) {
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; CHECK-LABEL: cntp_b64:
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; CHECK: cntp x0, p0, p1.d
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; CHECK-NEXT: ret
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%out = call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %pg,
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<vscale x 2 x i1> %a)
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ret i64 %out
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}
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declare i64 @llvm.aarch64.sve.cntb(i32 %pattern)
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declare i64 @llvm.aarch64.sve.cnth(i32 %pattern)
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declare i64 @llvm.aarch64.sve.cntw(i32 %pattern)
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declare i64 @llvm.aarch64.sve.cntd(i32 %pattern)
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declare i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
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declare i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
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declare i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
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declare i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>)
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