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I have added a new file: llvm/test/CodeGen/AArch64/README that describes what to do in the event one of the SVE codegen tests fails the warnings check. In addition, I've added comments to all the relevant SVE tests pointing users at the README file. Differential Revision: https://reviews.llvm.org/D83467
102 lines
2.7 KiB
LLVM
102 lines
2.7 KiB
LLVM
; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve --asm-verbose=false < %s 2>%t |FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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declare i32 @llvm.vscale.i32()
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declare i64 @llvm.vscale.i64()
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; Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)).
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define i64 @combine_add_vscale_i64() nounwind {
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; CHECK-LABEL: combine_add_vscale_i64:
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; CHECK-NOT: add
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; CHECK-NEXT: cntd x0
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; CHECK-NEXT: ret
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%vscale = call i64 @llvm.vscale.i64()
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%add = add i64 %vscale, %vscale
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ret i64 %add
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}
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define i32 @combine_add_vscale_i32() nounwind {
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; CHECK-LABEL: combine_add_vscale_i32:
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; CHECK-NOT: add
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; CHECK-NEXT: cntd x0
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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%add = add i32 %vscale, %vscale
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ret i32 %add
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}
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; Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)).
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; In this test, C0 = 1, C1 = 32.
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define i64 @combine_mul_vscale_i64() nounwind {
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; CHECK-LABEL: combine_mul_vscale_i64:
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; CHECK-NOT: mul
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; CHECK-NEXT: rdvl x0, #2
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; CHECK-NEXT: ret
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%vscale = call i64 @llvm.vscale.i64()
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%mul = mul i64 %vscale, 32
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ret i64 %mul
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}
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define i32 @combine_mul_vscale_i32() nounwind {
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; CHECK-LABEL: combine_mul_vscale_i32:
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; CHECK-NOT: mul
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; CHECK-NEXT: rdvl x0, #3
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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%mul = mul i32 %vscale, 48
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ret i32 %mul
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}
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; Canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C))
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define i64 @combine_sub_vscale_i64(i64 %in) nounwind {
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; CHECK-LABEL: combine_sub_vscale_i64:
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; CHECK-NOT: sub
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; CHECK-NEXT: rdvl x8, #-1
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; CHECK-NEXT: asr x8, x8, #4
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; CHECK-NEXT: add x0, x0, x8
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; CHECK-NEXT: ret
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%vscale = call i64 @llvm.vscale.i64()
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%sub = sub i64 %in, %vscale
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ret i64 %sub
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}
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define i32 @combine_sub_vscale_i32(i32 %in) nounwind {
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; CHECK-LABEL: combine_sub_vscale_i32:
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; CHECK-NOT: sub
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; CHECK-NEXT: rdvl x8, #-1
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; CHECK-NEXT: asr x8, x8, #4
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; CHECK-NEXT: add w0, w0, w8
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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%sub = sub i32 %in, %vscale
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ret i32 %sub
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}
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; Fold (shl (vscale * C0), C1) to (vscale * (C0 << C1)).
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; C0 = 1 , C1 = 4
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; At IR level, %shl = 2^4 * VSCALE.
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; At Assembly level, the output of RDVL is also 2^4 * VSCALE.
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; Hence, the immediate for RDVL is #1.
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define i64 @combine_shl_vscale_i64() nounwind {
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; CHECK-LABEL: combine_shl_vscale_i64:
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; CHECK-NOT: shl
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; CHECK-NEXT: rdvl x0, #1
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; CHECK-NEXT: ret
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%vscale = call i64 @llvm.vscale.i64()
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%shl = shl i64 %vscale, 4
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ret i64 %shl
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}
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define i32 @combine_shl_vscale_i32() nounwind {
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; CHECK-LABEL: combine_shl_vscale_i32:
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; CHECK-NOT: shl
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; CHECK-NEXT: rdvl x0, #1
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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%shl = shl i32 %vscale, 4
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ret i32 %shl
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}
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