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32e1c9e6be
If we wait until the type is legalized, we'll lose information about the orginal type and need to use larger magic constants. This gets especially bad on RISCV64 where i64 is the only legal type. I've limited this to simple scalar types so it only works for i8/i16/i32 which are most likely to occur. For more odd types we might want to do a small promotion to a type where MULH is legal instead. Unfortunately, this does prevent some urem/srem+seteq matching since that still require legal types. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D96210
246 lines
6.5 KiB
LLVM
246 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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define i1 @t32_3_1(i32 %X) nounwind {
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; CHECK-LABEL: t32_3_1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: mov w9, #1431655765
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; CHECK-NEXT: madd w8, w0, w8, w9
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 3
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%cmp = icmp eq i32 %urem, 1
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ret i1 %cmp
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}
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define i1 @t32_3_2(i32 %X) nounwind {
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; CHECK-LABEL: t32_3_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: mov w9, #-1431655766
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; CHECK-NEXT: madd w8, w0, w8, w9
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; CHECK-NEXT: mov w9, #1431655765
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 3
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%cmp = icmp eq i32 %urem, 2
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ret i1 %cmp
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}
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define i1 @t32_5_1(i32 %X) nounwind {
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; CHECK-LABEL: t32_5_1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #52429
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; CHECK-NEXT: movk w8, #52428, lsl #16
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; CHECK-NEXT: mov w9, #858993459
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; CHECK-NEXT: madd w8, w0, w8, w9
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 5
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%cmp = icmp eq i32 %urem, 1
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ret i1 %cmp
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}
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define i1 @t32_5_2(i32 %X) nounwind {
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; CHECK-LABEL: t32_5_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #52429
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; CHECK-NEXT: movk w8, #52428, lsl #16
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; CHECK-NEXT: mov w9, #1717986918
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; CHECK-NEXT: madd w8, w0, w8, w9
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; CHECK-NEXT: mov w9, #858993459
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 5
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%cmp = icmp eq i32 %urem, 2
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ret i1 %cmp
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}
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define i1 @t32_5_3(i32 %X) nounwind {
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; CHECK-LABEL: t32_5_3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #52429
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; CHECK-NEXT: movk w8, #52428, lsl #16
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; CHECK-NEXT: mov w9, #-1717986919
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; CHECK-NEXT: madd w8, w0, w8, w9
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; CHECK-NEXT: mov w9, #858993459
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 5
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%cmp = icmp eq i32 %urem, 3
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ret i1 %cmp
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}
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define i1 @t32_5_4(i32 %X) nounwind {
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; CHECK-LABEL: t32_5_4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #52429
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; CHECK-NEXT: movk w8, #52428, lsl #16
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; CHECK-NEXT: mov w9, #-858993460
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; CHECK-NEXT: madd w8, w0, w8, w9
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; CHECK-NEXT: mov w9, #858993459
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 5
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%cmp = icmp eq i32 %urem, 4
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ret i1 %cmp
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}
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define i1 @t32_6_1(i32 %X) nounwind {
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; CHECK-LABEL: t32_6_1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: mov w9, #1431655765
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; CHECK-NEXT: madd w8, w0, w8, w9
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; CHECK-NEXT: mov w9, #43691
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; CHECK-NEXT: ror w8, w8, #1
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; CHECK-NEXT: movk w9, #10922, lsl #16
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 6
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%cmp = icmp eq i32 %urem, 1
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ret i1 %cmp
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}
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define i1 @t32_6_2(i32 %X) nounwind {
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; CHECK-LABEL: t32_6_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: mov w9, #-1431655766
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; CHECK-NEXT: madd w8, w0, w8, w9
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; CHECK-NEXT: mov w9, #43691
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; CHECK-NEXT: ror w8, w8, #1
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; CHECK-NEXT: movk w9, #10922, lsl #16
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 6
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%cmp = icmp eq i32 %urem, 2
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ret i1 %cmp
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}
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define i1 @t32_6_3(i32 %X) nounwind {
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; CHECK-LABEL: t32_6_3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: mul w8, w0, w8
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; CHECK-NEXT: sub w8, w8, #1 // =1
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; CHECK-NEXT: mov w9, #43691
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; CHECK-NEXT: ror w8, w8, #1
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; CHECK-NEXT: movk w9, #10922, lsl #16
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 6
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%cmp = icmp eq i32 %urem, 3
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ret i1 %cmp
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}
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define i1 @t32_6_4(i32 %X) nounwind {
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; CHECK-LABEL: t32_6_4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: mov w9, #21844
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: movk w9, #21845, lsl #16
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; CHECK-NEXT: madd w8, w0, w8, w9
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; CHECK-NEXT: mov w9, #43690
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; CHECK-NEXT: ror w8, w8, #1
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; CHECK-NEXT: movk w9, #10922, lsl #16
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 6
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%cmp = icmp eq i32 %urem, 4
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ret i1 %cmp
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}
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define i1 @t32_6_5(i32 %X) nounwind {
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; CHECK-LABEL: t32_6_5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: mov w9, #43689
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: movk w9, #43690, lsl #16
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; CHECK-NEXT: madd w8, w0, w8, w9
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; CHECK-NEXT: mov w9, #43690
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; CHECK-NEXT: ror w8, w8, #1
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; CHECK-NEXT: movk w9, #10922, lsl #16
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 6
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%cmp = icmp eq i32 %urem, 5
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ret i1 %cmp
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}
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;-------------------------------------------------------------------------------
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; Other widths.
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define i1 @t16_3_2(i16 %X) nounwind {
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; CHECK-LABEL: t16_3_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: mov w9, #43691
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; CHECK-NEXT: mul w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #17
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; CHECK-NEXT: add w8, w8, w8, lsl #1
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; CHECK-NEXT: sub w8, w0, w8
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; CHECK-NEXT: and w8, w8, #0xffff
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; CHECK-NEXT: cmp w8, #2 // =2
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%urem = urem i16 %X, 3
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%cmp = icmp eq i16 %urem, 2
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ret i1 %cmp
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}
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define i1 @t8_3_2(i8 %X) nounwind {
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; CHECK-LABEL: t8_3_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xff
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; CHECK-NEXT: mov w9, #171
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; CHECK-NEXT: mul w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #9
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; CHECK-NEXT: add w8, w8, w8, lsl #1
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; CHECK-NEXT: sub w8, w0, w8
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; CHECK-NEXT: and w8, w8, #0xff
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; CHECK-NEXT: cmp w8, #2 // =2
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%urem = urem i8 %X, 3
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%cmp = icmp eq i8 %urem, 2
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ret i1 %cmp
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}
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define i1 @t64_3_2(i64 %X) nounwind {
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; CHECK-LABEL: t64_3_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #-6148914691236517206
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; CHECK-NEXT: movk x8, #43691
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; CHECK-NEXT: mov x9, #-6148914691236517206
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; CHECK-NEXT: madd x8, x0, x8, x9
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; CHECK-NEXT: mov x9, #6148914691236517205
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; CHECK-NEXT: cmp x8, x9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i64 %X, 3
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%cmp = icmp eq i64 %urem, 2
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ret i1 %cmp
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}
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