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https://github.com/RPCS3/llvm-mirror.git
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60121ef575
Prefer to keep uniform (non-divergent) multiplies on the scalar ALU when possible. This significantly improves some game cases by eliminating v_readfirstlane instructions when the result feeds into a scalar operation, like the address calculation for a scalar load or store. Since isDivergent is only an approximation of whether a value is in SGPRs, it can potentially regress some situations where a uniform value ends up in a VGPR. These should be rare in real code, although the test changes do contain a number of examples. Most of the test changes are just using s_mul instead of v_mul/mad which is generally better for both register pressure and latency (at least on GFX10 where sgpr pressure doesn't affect occupancy and vector ALU instructions have significantly longer latency than scalar ALU). Some R600 tests now use MULLO_INT instead of MUL_UINT24. GlobalISel appears to handle more scenarios in the desirable way, although it can also be thrown off and fails to select the 24-bit multiplies in some cases. Alternative solution considered and rejected was to allow selecting MUL_[UI]24 to S_MUL_I32. I've rejected this because the definition of those SD operations works is don't-care on the most significant 8 bits, and this fact is used in some combines via SimplifyDemandedBits. Based on a patch by Nicolai Hähnle. Differential Revision: https://reviews.llvm.org/D97063
185 lines
6.4 KiB
LLVM
185 lines
6.4 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=SI,GCN,SI-NOHSA,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=VI,VI-NOHSA,GCN,FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s
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; FUNC-LABEL: {{^}}local_size_x:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV * [[VAL]], KC0[1].Z
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
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; CI-HSA: s_load_dword [[XY:s[0-9]+]], s[4:5], 0x1
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; VI-HSA: s_load_dword [[XY:s[0-9]+]], s[4:5], 0x4
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define amdgpu_kernel void @local_size_x(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_y:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV * [[VAL]], KC0[1].W
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define amdgpu_kernel void @local_size_y(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_z:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV * [[VAL]], KC0[2].X
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define amdgpu_kernel void @local_size_z(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_xy:
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; SI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x6
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; SI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x7
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; VI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x18
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; VI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x1c
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; GCN: s_mul_i32 [[VAL:s[0-9]+]], [[X]], [[Y]]
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define amdgpu_kernel void @local_size_xy(i32 addrspace(1)* %out) {
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entry:
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%x = call i32 @llvm.r600.read.local.size.x() #0
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%y = call i32 @llvm.r600.read.local.size.y() #0
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%val = mul i32 %x, %y
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_xz:
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; SI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x6
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; SI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x8
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; VI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x18
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; VI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x20
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; HSA-DAG: s_and_b32 [[X:s[0-9]+]], [[XY]], 0xffff
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; GCN: s_mul_i32 [[VAL:s[0-9]+]], [[X]], [[Z]]
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define amdgpu_kernel void @local_size_xz(i32 addrspace(1)* %out) {
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entry:
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%x = call i32 @llvm.r600.read.local.size.x() #0
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%z = call i32 @llvm.r600.read.local.size.z() #0
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%val = mul i32 %x, %z
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_yz:
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 1
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; SI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x7
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; SI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x8
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; VI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x1c
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; VI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x20
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; GCN: s_mul_i32 [[VAL:s[0-9]+]], [[Y]], [[Z]]
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define amdgpu_kernel void @local_size_yz(i32 addrspace(1)* %out) {
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entry:
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%y = call i32 @llvm.r600.read.local.size.y() #0
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%z = call i32 @llvm.r600.read.local.size.z() #0
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%val = mul i32 %y, %z
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_xyz:
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 1
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; SI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x6
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; SI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x7
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; SI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x8
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; VI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x18
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; VI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x1c
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; VI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x20
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; GCN: s_mul_i32 [[M:s[0-9]+]], [[X]], [[Y]]
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; GCN: s_add_i32 [[VAL:s[0-9]+]], [[M]], [[Z]]
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; GCN-DAG: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define amdgpu_kernel void @local_size_xyz(i32 addrspace(1)* %out) {
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entry:
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%x = call i32 @llvm.r600.read.local.size.x() #0
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%y = call i32 @llvm.r600.read.local.size.y() #0
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%z = call i32 @llvm.r600.read.local.size.z() #0
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%xy = mul i32 %x, %y
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%xyz = add i32 %xy, %z
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store i32 %xyz, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_x_known_bits:
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
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; GCN-NOT: 0xffff
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NEXT: buffer_store_dword [[VVAL]]
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define amdgpu_kernel void @local_size_x_known_bits(i32 addrspace(1)* %out) {
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entry:
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%size = call i32 @llvm.r600.read.local.size.x() #0
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%shl = shl i32 %size, 16
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%shr = lshr i32 %shl, 16
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store i32 %shr, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_y_known_bits:
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
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; GCN-NOT: 0xffff
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NEXT: buffer_store_dword [[VVAL]]
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define amdgpu_kernel void @local_size_y_known_bits(i32 addrspace(1)* %out) {
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entry:
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%size = call i32 @llvm.r600.read.local.size.y() #0
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%shl = shl i32 %size, 16
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%shr = lshr i32 %shl, 16
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store i32 %shr, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_z_known_bits:
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20
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; GCN-NOT: 0xffff
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NEXT: buffer_store_dword [[VVAL]]
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define amdgpu_kernel void @local_size_z_known_bits(i32 addrspace(1)* %out) {
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entry:
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%size = call i32 @llvm.r600.read.local.size.z() #0
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%shl = shl i32 %size, 16
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%shr = lshr i32 %shl, 16
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store i32 %shr, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.r600.read.local.size.x() #0
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declare i32 @llvm.r600.read.local.size.y() #0
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declare i32 @llvm.r600.read.local.size.z() #0
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attributes #0 = { nounwind readnone }
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