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llvm-mirror/test/CodeGen/AMDGPU/loop_header_nopred.mir
Guozhi Wei 2be00d9e54 [MBP] Avoid tail duplication if it can't bring benefit
Current tail duplication integrated in bb layout is designed to increase the fallthrough from a BB's predecessor to its successor, but we have observed cases that duplication doesn't increase fallthrough, or it brings too much size overhead.

To overcome these two issues in function canTailDuplicateUnplacedPreds I add two checks:

  make sure there is at least one duplication in current work set.
  the number of duplication should not exceed the number of successors.

The modification in hasBetterLayoutPredecessor fixes a bug that potential predecessor must be at the bottom of a chain.

Differential Revision: https://reviews.llvm.org/D64376
2019-12-06 09:53:53 -08:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -o - -run-pass=block-placement -mcpu=gfx1010 -mattr=-inst-fwd-prefetch-bug -verify-machineinstrs %s | FileCheck -check-prefix=GCN %s
# Used to fail with
# Assertion `Out && "Header of loop has no predecessors from outside loop?"
---
name: loop_header_nopred
body: |
; GCN-LABEL: name: loop_header_nopred
; GCN: bb.0:
; GCN: successors: %bb.1(0x80000000)
; GCN: S_INST_PREFETCH 1
; GCN: S_BRANCH %bb.1
; GCN: bb.6 (align 64):
; GCN: successors: %bb.7(0x04000000), %bb.1(0x7c000000)
; GCN: S_CBRANCH_VCCNZ %bb.7, implicit $vcc
; GCN: bb.1:
; GCN: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; GCN: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
; GCN: bb.3:
; GCN: successors: %bb.4(0x40000000), %bb.6(0x40000000)
; GCN: SI_MASK_BRANCH %bb.6, implicit $exec
; GCN: S_BRANCH %bb.4
; GCN: bb.2 (align 64):
; GCN: successors: %bb.4(0x40000000), %bb.6(0x40000000)
; GCN: SI_MASK_BRANCH %bb.6, implicit $exec
; GCN: S_BRANCH %bb.4
; GCN: bb.4:
; GCN: successors: %bb.5(0x04000000), %bb.4(0x7c000000)
; GCN: S_NOP 0
; GCN: S_NOP 0
; GCN: S_NOP 0
; GCN: S_NOP 0
; GCN: S_NOP 0
; GCN: S_NOP 0
; GCN: S_NOP 0
; GCN: S_NOP 0
; GCN: S_NOP 0
; GCN: S_NOP 0
; GCN: S_NOP 0
; GCN: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN: bb.5:
; GCN: successors: %bb.6(0x80000000)
; GCN: S_BRANCH %bb.6
; GCN: bb.7:
; GCN: S_ENDPGM 0
bb.0:
successors: %bb.1(0x80000000)
bb.1:
successors: %bb.2(0x40000000), %bb.3(0x40000000)
S_CBRANCH_VCCZ %bb.3, implicit $vcc
S_BRANCH %bb.2
bb.2:
successors: %bb.3(0x80000000)
bb.3:
successors: %bb.4(0x40000000), %bb.6(0x40000000)
SI_MASK_BRANCH %bb.6, implicit $exec
S_BRANCH %bb.4
bb.4:
successors: %bb.5(0x04000000), %bb.4(0x7c000000)
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
S_CBRANCH_EXECZ %bb.4, implicit $exec
bb.5:
successors: %bb.6(0x80000000)
bb.6:
successors: %bb.7(0x04000000), %bb.1(0x7c000000)
S_CBRANCH_VCCZ %bb.1, implicit $vcc
bb.7:
S_ENDPGM 0
...