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59de807f62
This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
32 lines
933 B
YAML
32 lines
933 B
YAML
# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa-opencl -run-pass=simple-register-coalescing | FileCheck %s
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---
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# Checks for a bug where subregister liveranges were not properly pruned for
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# an IMPLCITI_DEF that gets removed completely.
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#
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# CHECK-LABEL: name: func
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# IMPLICIT_DEF should be gone without llc hitting assertion failures.
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# CHECK-NOT: IMPLICIT_DEF
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name: func
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tracksRegLiveness: true
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body: |
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bb.0:
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undef %5.sub1 = V_MOV_B32_e32 0, implicit $exec
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%6 = COPY %5
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S_CBRANCH_VCCZ %bb.2, implicit undef $vcc
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bb.1:
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%1 : sreg_32_xm0 = S_MOV_B32 0
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undef %0.sub0 : sreg_64 = COPY %1
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%0.sub1 = COPY %1
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%4 : vreg_64 = COPY killed %0
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%5 : vreg_64 = IMPLICIT_DEF
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%6 : vreg_64 = COPY killed %4
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bb.2:
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%2 : vgpr_32 = V_CVT_F32_I32_e32 killed %5.sub1, implicit $mode, implicit $exec
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bb.3:
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%3 : vgpr_32 = V_CVT_F32_I32_e32 killed %6.sub1, implicit $mode, implicit $exec
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S_ENDPGM 0
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...
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