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8a74c287ae
This is a (last big?) part of the patch series to make SimplifyCFG
preserve DomTree. Currently, it still does not actually preserve it,
even thought it is pretty much fully updated to preserve it.
Once the default is flipped, a valid DomTree must be passed into
simplifyCFG, which means that whatever pass calls simplifyCFG,
should also be smart about DomTree's.
As far as i can see from `check-llvm` with default flipped,
this is the last LLVM test batch (other than bugpoint tests)
that needed fixes to not break with default flipped.
The changes here are boringly identical to the ones i did
over 42+ times/commits recently already,
so while AMDGPU is outside of my normal ecosystem,
i'm going to go for post-commit review here,
like in all the other 42+ changes.
Note that while the pass is taught to preserve {,Post}DomTree,
it still doesn't do that by default, because simplifycfg
still doesn't do that by default, and flipping default
in this pass will implicitly flip the default for simplifycfg.
That will happen, but not right now.
79 lines
2.0 KiB
LLVM
79 lines
2.0 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator:
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; GCN: v_cmp_eq_u32
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; GCN: s_and_saveexec_b64
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; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %unreachable
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; GCN: ds_write_b32
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; GCN: ; divergent unreachable
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; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %UnifiedReturnBlock
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; GCN: s_endpgm
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define amdgpu_kernel void @lower_control_flow_unreachable_terminator() #0 {
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bb:
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%tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y()
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%tmp63 = icmp eq i32 %tmp15, 32
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br i1 %tmp63, label %unreachable, label %ret
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unreachable:
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store volatile i32 0, i32 addrspace(3)* undef, align 4
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unreachable
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator_swap_block_order:
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; GCN: v_cmp_ne_u32
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; GCN: s_and_saveexec_b64
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; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %unreachable
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; GCN: ds_write_b32
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; GCN: ; divergent unreachable
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; GCN: ; %bb.{{[0-9]+}}:
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @lower_control_flow_unreachable_terminator_swap_block_order() #0 {
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bb:
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%tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y()
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%tmp63 = icmp eq i32 %tmp15, 32
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br i1 %tmp63, label %ret, label %unreachable
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ret:
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ret void
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unreachable:
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store volatile i32 0, i32 addrspace(3)* undef, align 4
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unreachable
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}
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; GCN-LABEL: {{^}}uniform_lower_control_flow_unreachable_terminator:
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; GCN: s_cmp_lg_u32
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; GCN: s_cbranch_scc0 [[UNREACHABLE:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: %bb.{{[0-9]+}}: ; %ret
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; GCN-NEXT: s_endpgm
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; GCN: [[UNREACHABLE]]:
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; GCN: ds_write_b32
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define amdgpu_kernel void @uniform_lower_control_flow_unreachable_terminator(i32 %arg0) #0 {
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bb:
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%tmp63 = icmp eq i32 %arg0, 32
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br i1 %tmp63, label %unreachable, label %ret
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unreachable:
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store volatile i32 0, i32 addrspace(3)* undef, align 4
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unreachable
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ret:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.y() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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