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f1ba6f4d9b
gfx90a operations require even aligned registers, but this was previously achieved by reserving registers inside the full class. Ideally this would be captured in the static instruction definitions for the operands, and we would have different instructions per subtarget. The hackiest part of this is we need to manually reassign AGPR register classes after instruction selection (we get away without this for VGPRs since those types are actually registered for legal types).
187 lines
5.7 KiB
YAML
187 lines
5.7 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx90a %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: test_fmamk_reg_imm_f64
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# GCN: V_FMA_F64_e64 0, killed %0, 0, %2, 0, killed %1, 0, 0, implicit $mode, implicit $exec
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---
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name: test_fmamk_reg_imm_f64
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registers:
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- { id: 0, class: vreg_64_align2 }
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- { id: 1, class: vreg_64_align2 }
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- { id: 2, class: vreg_64_align2 }
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- { id: 3, class: vreg_64_align2 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = COPY %0
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%2 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
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%3 = V_FMAC_F64_e32 killed %0, %2, killed %1, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: test_fmamk_imm_reg_f64
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# GCN: V_FMA_F64_e64 0, %2, 0, killed %0.sub0_sub1, 0, killed %1, 0, 0, implicit $mode, implicit $exec
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---
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name: test_fmamk_imm_reg_f64
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registers:
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- { id: 0, class: vreg_128_align2 }
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- { id: 1, class: vreg_64_align2 }
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- { id: 2, class: vreg_64_align2 }
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- { id: 3, class: vreg_64_align2 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = COPY %0.sub2_sub3
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%2 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
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%3 = V_FMAC_F64_e32 %2, killed %0.sub0_sub1, killed %1, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: test_fmaak_f64
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# GCN: V_FMA_F64_e64 0, killed %0.sub0_sub1, 0, %0.sub2_sub3, 0, %1, 0, 0, implicit $mode, implicit $exec
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---
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name: test_fmaak_f64
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registers:
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- { id: 0, class: vreg_128_align2 }
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- { id: 1, class: vreg_64_align2 }
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- { id: 2, class: vreg_64_align2 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
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%2 = V_FMAC_F64_e32 killed %0.sub0_sub1, %0.sub2_sub3, %1, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: test_fmaak_sgpr_src0_f64
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# GCN: V_FMA_F64_e64 0, killed %0, 0, %1, 0, %2:vreg_64_align2, 0, 0, implicit $mode, implicit $exec
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---
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name: test_fmaak_sgpr_src0_f64
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registers:
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- { id: 0, class: sreg_64 }
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- { id: 1, class: vreg_64_align2 }
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- { id: 2, class: vreg_64_align2 }
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- { id: 3, class: vreg_64_align2 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
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%3 = V_FMAC_F64_e32 killed %0, %1, %2, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: test_fmaak_inlineimm_src0_f64
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# GCN: V_FMA_F64_e64 0, 4611686018427387904, 0, %0, 0, %1:vreg_64_align2, 0, 0, implicit $mode, implicit $exec
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---
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name: test_fmaak_inlineimm_src0_f64
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registers:
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- { id: 0, class: vreg_64_align2 }
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- { id: 1, class: vreg_64_align2 }
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- { id: 2, class: vreg_64_align2 }
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body: |
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bb.0:
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%0 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
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%2 = V_FMAC_F64_e32 4611686018427387904, %0, %1, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: test_fmaak_otherimm_src0_f64
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# GCN: V_FMA_F64_e64 0, 4611686018427387904, 0, %0, 0, %1:vreg_64_align2, 0, 0, implicit $mode, implicit $exec
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---
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name: test_fmaak_otherimm_src0_f64
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registers:
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- { id: 0, class: vreg_64_align2 }
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- { id: 1, class: vreg_64_align2 }
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- { id: 2, class: vreg_64_align2 }
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body: |
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bb.0:
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%0 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
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%2 = V_FMAC_F64_e32 4611686018427387904, %0, %1, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: test_fmaak_other_constantlike_src0_f64
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# GCN: V_FMAC_F64_e32 %stack.0, %0, %2, implicit $mode, implicit $exec
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---
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name: test_fmaak_other_constantlike_src0_f64
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registers:
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- { id: 0, class: vreg_64_align2 }
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- { id: 1, class: vreg_64_align2 }
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- { id: 2, class: vreg_64_align2 }
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stack:
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- { id: 0, name: "", type: default, offset: 0, size: 128, alignment: 8,
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callee-saved-register: '', local-offset: 0, debug-info-variable: '',
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debug-info-expression: '', debug-info-location: '' }
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body: |
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bb.0:
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%0 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
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%2 = V_FMAC_F64_e32 %stack.0, %0, %1, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: test_fmamk_reg_unfoldable_literal_src0_f64
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# GCN: V_FMA_F64_e64 0, %2, 0, killed %0, 0, killed %1, 0, 0, implicit $mode, implicit $exec
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---
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name: test_fmamk_reg_unfoldable_literal_src0_f64
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registers:
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- { id: 0, class: vreg_64_align2 }
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- { id: 1, class: vreg_64_align2 }
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- { id: 2, class: vreg_64_align2 }
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- { id: 3, class: vreg_64_align2 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = COPY %0
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%2 = V_MOV_B64_PSEUDO 123456, implicit $exec
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%3 = V_FMAC_F64_e32 %2, killed %0, killed %1, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: test_fmamk_reg_unfoldable_literal_src1_f64
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# GCN: V_FMA_F64_e64 0, killed %0, 0, %2, 0, killed %1, 0, 0, implicit $mode, implicit $exec
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---
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name: test_fmamk_reg_unfoldable_literal_src1_f64
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registers:
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- { id: 0, class: vreg_64_align2 }
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- { id: 1, class: vreg_64_align2 }
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- { id: 2, class: vreg_64_align2 }
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- { id: 3, class: vreg_64_align2 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = COPY %0
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%2 = V_MOV_B64_PSEUDO 123456, implicit $exec
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%3 = V_FMAC_F64_e32 killed %0, %2, killed %1, implicit $mode, implicit $exec
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...
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# GCN-LABEL: name: test_fmaak_reg_unfoldable_literal_src2_f64
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# GCN: V_FMA_F64_e64 0, killed %0, 0, killed %1, 0, %2, 0, 0, implicit $mode, implicit $exec
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---
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name: test_fmaak_reg_unfoldable_literal_src2_f64
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registers:
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- { id: 0, class: vreg_64_align2 }
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- { id: 1, class: vreg_64_align2 }
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- { id: 2, class: vreg_64_align2 }
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- { id: 3, class: vreg_64_align2 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = COPY %0
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%2 = V_MOV_B64_PSEUDO 123456, implicit $exec
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%3 = V_FMAC_F64_e32 killed %0, killed %1, %2, implicit $mode, implicit $exec
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...
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