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dd02e99d65
This handles the last case of the builtin function calls that we would
generate code which differed from Microsoft's ABI. Rather than
generating a call to `__pow{d,s}i2` we now promote the parameter to a
float or double and invoke `powf` or `pow` instead.
Addresses PR30825!
llvm-svn: 286082
58 lines
1.4 KiB
LLVM
58 lines
1.4 KiB
LLVM
; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s
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declare double @llvm.powi.f64(double, i32)
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declare float @llvm.powi.f32(float, i32)
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define arm_aapcs_vfpcc double @d(double %d, i32 %i) {
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entry:
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%0 = tail call double @llvm.powi.f64(double %d, i32 %i)
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ret double %0
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}
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; CHECK-LABEL: d:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
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; CHECK-NEXT: b pow
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; CHECK-NOT: __powisf2
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define arm_aapcs_vfpcc float @f(float %f, i32 %i) {
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entry:
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%0 = tail call float @llvm.powi.f32(float %f, i32 %i)
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ret float %0
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}
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; CHECK-LABEL: f:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
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; CHECK-NEXT: b pow
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; CHECK-NOT: __powisf2
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define arm_aapcs_vfpcc float @g(double %d, i32 %i) {
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entry:
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%0 = tail call double @llvm.powi.f64(double %d, i32 %i)
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%conv = fptrunc double %0 to float
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ret float %conv
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}
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; CHECK-LABEL: g:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
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; CHECK-NEXT: bl pow
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; CHECK-NOT: bl __powidf2
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; CHECK-NEXT: vcvt.f32.f64 s0, d0
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define arm_aapcs_vfpcc double @h(float %f, i32 %i) {
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entry:
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%0 = tail call float @llvm.powi.f32(float %f, i32 %i)
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%conv = fpext float %0 to double
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ret double %conv
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}
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; CHECK-LABEL: h:
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; CHECK: vmov s[[REGISTER:[0-9]+]], r0
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; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
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; CHECK-NEXT: bl powf
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; CHECK-NOT: bl __powisf2
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; CHECK-NEXT: vcvt.f64.f32 d0, s0
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