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llvm-mirror/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
Matt Arsenault fcf8b40603 MIR: Infer not-SSA for subregister defs
It's possible to have a single virtual register def with a subreg
index that would pass the previous check, but it's not possible to
have a subregister def in SSA.

This is in preparation for adding stricter checks for SSA MIR.
2020-08-27 16:56:16 -04:00

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# REQUIRES: asserts
# RUN: not --crash llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: MachineFunctionProperties required by InstructionSelect pass are not met by function subreg_def_is_not_ssa.
# CHECK-NEXT: Required properties: IsSSA
# CHECK-NEXT: Current properties: NoPHIs
# CHECK-NEXT: MachineFunctionProperties check failed
---
name: subreg_def_is_not_ssa
body: |
bb.0:
%0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
...