mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
d5cb6187da
This patch is the initial patch for support of the AIX extended vector ABI. The extended ABI treats vector registers V20-V31 as non-volatile and we add them as callee saved registers in this patch. Reviewed By: sfertile Differential Revision: https://reviews.llvm.org/D88676
49 lines
1.2 KiB
LLVM
49 lines
1.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
|
|
; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL
|
|
|
|
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
|
|
; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE
|
|
|
|
@a = common global i32 0
|
|
|
|
define i32 @test_load() {
|
|
entry:
|
|
%0 = load i32, i32* @a
|
|
ret i32 %0
|
|
}
|
|
|
|
; SMALL-LABEL: .test_load:{{$}}
|
|
; SMALL: lwz [[REG1:[0-9]+]], L..C0(2)
|
|
; SMALL: lwz [[REG2:[0-9]+]], 0([[REG1]])
|
|
; SMALL: blr
|
|
|
|
; LARGE-LABEL: .test_load:{{$}}
|
|
; LARGE: addis [[REG1:[0-9]+]], L..C0@u(2)
|
|
; LARGE: lwz [[REG2:[0-9]+]], L..C0@l([[REG1]])
|
|
; LARGE: lwz [[REG3:[0-9]+]], 0([[REG2]])
|
|
; LARGE: blr
|
|
|
|
@b = common global i32 0
|
|
|
|
define void @test_store(i32 %0) {
|
|
store i32 %0, i32* @b
|
|
ret void
|
|
}
|
|
|
|
; SMALL-LABEL: .test_store:{{$}}
|
|
; SMALL: lwz [[REG1:[0-9]+]], L..C1(2)
|
|
; SMALL: stw [[REG2:[0-9]+]], 0([[REG1]])
|
|
; SMALL: blr
|
|
|
|
; LARGE-LABEL: .test_store:{{$}}
|
|
; LARGE: addis [[REG1:[0-9]+]], L..C1@u(2)
|
|
; LARGE: lwz [[REG2:[0-9]+]], L..C1@l([[REG1]])
|
|
; LARGE: stw [[REG3:[0-9]+]], 0([[REG2]])
|
|
; LARGE: blr
|
|
|
|
; SMALL: .tc a[TC],a
|
|
; SMALL: .tc b[TC],b
|
|
|
|
; LARGE: .tc a[TE],a
|
|
; LARGE: .tc b[TE],b
|