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d49cb60862
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
91 lines
3.7 KiB
YAML
91 lines
3.7 KiB
YAML
# RUN: llc %s -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=postmisched \
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# RUN: -debug-only=machine-scheduler -o - 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# Test that the cycle index is the same before and after scheduling an
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# instruction with 6 decoder slots.
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# CHECK: ++ | Current cycle index: 3
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# CHECK-NEXT: ++ | Resource counters: Z13_FXaUnit:2
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# CHECK-NEXT: ** ScheduleDAGMI::schedule picking next node
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# CHECK-NEXT: ** Available: {SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone, SU(6):LARL/FXa}
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# CHECK-NEXT: ** Best so far: SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone Grouping cost:-1 Height:43
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# CHECK-NEXT: ** Tried : SU(6):LARL/FXa Height:14
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# CHECK-NEXT: ** Scheduling SU(3) Grouping cost:-1
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# CHECK-NEXT: ++ HazardRecognizer emitting SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone
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# CHECK-NEXT: ++ Decode group before emission: <empty>
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# CHECK-NEXT: ++ Completed decode group: { SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone } (6 decoder slots)
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# CHECK-NEXT: ++ | Current decoder group: <empty>
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# CHECK-NEXT: ++ | Current cycle index: 3
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
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target triple = "s390x--linux-gnu"
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%0 = type { i8, i8, i8, i8, i16, i32, i32, i32 }
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@TTSize = external dso_local local_unnamed_addr global i32, align 4
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@AS_TTable = external dso_local local_unnamed_addr global %0*, align 8
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@Variant = external dso_local local_unnamed_addr global i32, align 4
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define dso_local void @LearnStoreTT(i32 signext %arg, i32 zeroext %arg1, i32 signext %arg2) #0 {
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bb:
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%tmp = load i32, i32* @TTSize, align 4
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%tmp3 = urem i32 %arg1, %tmp
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%tmp4 = load %0*, %0** @AS_TTable, align 8
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%tmp5 = zext i32 %tmp3 to i64
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%tmp6 = load i32, i32* @Variant, align 4
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%tmp7 = add i32 %tmp6, -3
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%tmp8 = icmp ugt i32 %tmp7, 1
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%tmp9 = select i1 %tmp8, i8 3, i8 1
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store i8 %tmp9, i8* undef, align 1
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store i32 %arg, i32* undef, align 4
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%tmp10 = trunc i32 %arg2 to i8
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store i8 %tmp10, i8* null, align 1
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%tmp11 = getelementptr inbounds %0, %0* %tmp4, i64 %tmp5, i32 2
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store i8 0, i8* %tmp11, align 2
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ret void
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}
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attributes #0 = { "target-cpu"="z13" }
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...
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---
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name: LearnStoreTT
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alignment: 16
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tracksRegLiveness: true
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liveins:
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- { reg: '$r2d' }
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- { reg: '$r3d' }
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- { reg: '$r4d' }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0.bb:
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liveins: $r2d, $r3d, $r4d
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$r1d = LGR $r3d, implicit-def $r0q
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renamable $r3d = LARL @TTSize
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renamable $r0d = LLILL 0, implicit killed $r0q, implicit-def $r0q
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renamable $r0q = DL killed renamable $r0q, killed renamable $r3d, 0, $noreg :: (dereferenceable load 4 from @TTSize)
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renamable $r3d = LGRL @AS_TTable :: (dereferenceable load 8 from @AS_TTable)
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renamable $r1d = LLGFR renamable $r0l, implicit killed $r0q
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renamable $r5d = LARL @Variant
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renamable $r0l = LHI -3
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renamable $r0l = A killed renamable $r0l, killed renamable $r5d, 0, $noreg, implicit-def dead $cc :: (dereferenceable load 4 from @Variant)
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CLFI killed renamable $r0l, 1, implicit-def $cc
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renamable $r0l = LHI 1
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renamable $r0l = LOCHI killed renamable $r0l, 3, 14, 2, implicit killed $cc
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STC killed renamable $r0l, undef renamable $r1d, 0, $noreg :: (store 1 into `i8* undef`)
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ST renamable $r2l, undef renamable $r1d, 0, $noreg, implicit killed $r2d :: (store 4 into `i32* undef`)
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STC renamable $r4l, $noreg, 0, $noreg, implicit killed $r4d :: (store 1 into `i8* null`)
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renamable $r1d = MGHI killed renamable $r1d, 20
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renamable $r0l = LHI 0
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STC killed renamable $r0l, killed renamable $r3d, 2, killed renamable $r1d :: (store 1 into %ir.tmp11, align 2)
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Return
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...
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