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55d27cdd65
Updated the scheduling information for the Haswell subtarget with the following changes: Regrouped the instructions after adding appropriate load + store latencies. Added scheduling for missing instructions such as the GATHER instrs. The changes were made after revisiting the latencies impact of all memory uOps. Reviewers: RKSimon, zvi, craig.topper, apilipenko Differential Revision: https://reviews.llvm.org/D40021 Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7 llvm-svn: 320137
49 lines
2.5 KiB
LLVM
49 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @f_fu(float* %ret, float* %aa, float %b) {
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; CHECK-LABEL: f_fu:
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; CHECK: ## %bb.0: ## %allocas
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; CHECK-NEXT: vcvttss2si %xmm0, %eax
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; CHECK-NEXT: vpbroadcastd %eax, %zmm0
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; CHECK-NEXT: vcvttps2dq (%rsi), %zmm1
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; CHECK-NEXT: vpsrld $31, %zmm0, %zmm2
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; CHECK-NEXT: vpaddd %zmm2, %zmm0, %zmm2
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; CHECK-NEXT: vpsrad $1, %zmm2, %zmm2
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; CHECK-NEXT: movw $-21846, %ax ## imm = 0xAAAA
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; CHECK-NEXT: kmovw %eax, %k1
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; CHECK-NEXT: vmovdqa32 {{.*}}(%rip), %zmm1 {%k1}
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; CHECK-NEXT: vpaddd %zmm0, %zmm2, %zmm0
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; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0
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; CHECK-NEXT: vcvtdq2ps %zmm0, %zmm0
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; CHECK-NEXT: vmovups %zmm0, (%rdi)
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; CHECK-NEXT: retq
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allocas:
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%ptr_cast_for_load = bitcast float* %aa to <16 x float>*
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%ptr_masked_load.39 = load <16 x float>, <16 x float>* %ptr_cast_for_load, align 4
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%b_load_to_int32 = fptosi float %b to i32
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%b_load_to_int32_broadcast_init = insertelement <16 x i32> undef, i32 %b_load_to_int32, i32 0
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%b_load_to_int32_broadcast = shufflevector <16 x i32> %b_load_to_int32_broadcast_init, <16 x i32> undef, <16 x i32> zeroinitializer
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%b_to_int32 = fptosi float %b to i32
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%b_to_int32_broadcast_init = insertelement <16 x i32> undef, i32 %b_to_int32, i32 0
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%b_to_int32_broadcast = shufflevector <16 x i32> %b_to_int32_broadcast_init, <16 x i32> undef, <16 x i32> zeroinitializer
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%a_load_to_int32 = fptosi <16 x float> %ptr_masked_load.39 to <16 x i32>
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%div_v019_load_ = sdiv <16 x i32> %b_to_int32_broadcast, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%v1.i = select <16 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>, <16 x i32> %a_load_to_int32
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%foo_test = add <16 x i32> %div_v019_load_, %b_load_to_int32_broadcast
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%add_struct_offset_y_struct_offset33_x = add <16 x i32> %foo_test, %v1.i
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%val = sitofp <16 x i32> %add_struct_offset_y_struct_offset33_x to <16 x float>
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%ptrcast = bitcast float* %ret to <16 x float>*
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store <16 x float> %val, <16 x float>* %ptrcast, align 4
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ret void
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}
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