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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
120 lines
3.1 KiB
LLVM
120 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
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define i32 @test1(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: cmpl $1, %edi
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; CHECK-NEXT: sbbl $-1, %eax
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; CHECK-NEXT: retq
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%not.cmp = icmp ne i32 %a, 0
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%inc = zext i1 %not.cmp to i32
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%retval.0 = add i32 %inc, %b
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ret i32 %retval.0
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}
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define i32 @test1_commute(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: test1_commute:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: cmpl $1, %edi
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; CHECK-NEXT: sbbl $-1, %eax
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; CHECK-NEXT: retq
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%cmp = icmp ne i32 %a, 0
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%inc = zext i1 %cmp to i32
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%ret = add i32 %b, %inc
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ret i32 %ret
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}
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define i32 @test2(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: cmpl $1, %edi
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; CHECK-NEXT: adcl $0, %eax
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; CHECK-NEXT: retq
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%cmp = icmp eq i32 %a, 0
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%inc = zext i1 %cmp to i32
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%retval.0 = add i32 %inc, %b
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ret i32 %retval.0
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}
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define i32 @test3(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: cmpl $1, %edi
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; CHECK-NEXT: adcl $0, %eax
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; CHECK-NEXT: retq
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%cmp = icmp eq i32 %a, 0
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%inc = zext i1 %cmp to i32
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%retval.0 = add i32 %inc, %b
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ret i32 %retval.0
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}
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define i32 @test4(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: cmpl $1, %edi
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; CHECK-NEXT: sbbl $-1, %eax
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; CHECK-NEXT: retq
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%not.cmp = icmp ne i32 %a, 0
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%inc = zext i1 %not.cmp to i32
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%retval.0 = add i32 %inc, %b
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ret i32 %retval.0
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}
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define i32 @test5(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: cmpl $1, %edi
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; CHECK-NEXT: adcl $-1, %eax
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; CHECK-NEXT: retq
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%not.cmp = icmp ne i32 %a, 0
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%inc = zext i1 %not.cmp to i32
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%retval.0 = sub i32 %b, %inc
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ret i32 %retval.0
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}
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define i32 @test6(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: cmpl $1, %edi
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; CHECK-NEXT: sbbl $0, %eax
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; CHECK-NEXT: retq
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%cmp = icmp eq i32 %a, 0
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%inc = zext i1 %cmp to i32
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%retval.0 = sub i32 %b, %inc
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ret i32 %retval.0
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}
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define i32 @test7(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: test7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: cmpl $1, %edi
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; CHECK-NEXT: sbbl $0, %eax
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; CHECK-NEXT: retq
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%cmp = icmp eq i32 %a, 0
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%inc = zext i1 %cmp to i32
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%retval.0 = sub i32 %b, %inc
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ret i32 %retval.0
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}
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define i32 @test8(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: test8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: cmpl $1, %edi
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; CHECK-NEXT: adcl $-1, %eax
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; CHECK-NEXT: retq
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%not.cmp = icmp ne i32 %a, 0
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%inc = zext i1 %not.cmp to i32
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%retval.0 = sub i32 %b, %inc
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ret i32 %retval.0
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}
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