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d094523cbe
We now only add +64bit to the CPU string for "generic" CPU. All other CPU names are assumed to have the feature flag already set if they support 64-bit. I've remove the implies from CMPXCHG8 so that Feature64Bit only comes in via CPUs or user passing -mattr=+64bit. I've changed the assert to a report_fatal_error so it's not lost in Release builds. The test updates are to fix things that tripped the new error. Differential Revision: https://reviews.llvm.org/D51231 llvm-svn: 341022
35 lines
1.0 KiB
LLVM
35 lines
1.0 KiB
LLVM
; RUN: llc < %s -x86-early-ifcvt -verify-machineinstrs
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; RUN: llc < %s -x86-early-ifcvt -stress-early-ifcvt -verify-machineinstrs
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; CPU without a scheduling model:
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; RUN: llc < %s -x86-early-ifcvt -mcpu=k8 -verify-machineinstrs
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;
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; Run these tests with and without -stress-early-ifcvt to exercise heuristics.
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;
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target triple = "x86_64-apple-macosx10.8.0"
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; MachineTraceMetrics::Ensemble::addLiveIns crashes because the first operand
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; on an inline asm instruction is not a vreg def.
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; <rdar://problem/12472811>
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define void @f1() nounwind {
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entry:
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br i1 undef, label %if.then6.i, label %if.end.i
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if.then6.i:
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br label %if.end.i
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if.end.i:
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br i1 undef, label %if.end25.i, label %if.else17.i
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if.else17.i:
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%shl24.i = shl i32 undef, undef
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br label %if.end25.i
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if.end25.i:
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%storemerge31.i = phi i32 [ %shl24.i, %if.else17.i ], [ 0, %if.end.i ]
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store i32 %storemerge31.i, i32* undef, align 4
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%0 = tail call i32 asm sideeffect "", "=r,r,i,i"(i32 undef, i32 15, i32 1) nounwind
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%conv = trunc i32 %0 to i8
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store i8 %conv, i8* undef, align 1
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unreachable
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}
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