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174fc0dbbe
The PREFETCHW instruction was originally part of the 3DNow. But it was given its own CPUID bit on later CPUs just before 3DNow was deprecated. We were setting the -mprfchw flag if -m3dnow was passed or the CPU supported 3dnow unless -mno-prfchw was passed. But -march=native on a CPU without the PRFCHW CPUID bit set will pass -mno-prfchw. So -march=k8 will behave differently than -march=native on a K8 for example. So remove this implicit setting from the frontend and instead enable the backend to use PREFETCHW if 3dnow OR prfchw is enabled. Also enable PRFCHW flag on amdfam10/barcelona which seems to be where this CPUID bit was introduced. That CPU also supported 3dnow.
89 lines
3.9 KiB
LLVM
89 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- -mattr=+sse | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prfchw | FileCheck %s -check-prefix=PRFCHWSSE
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; RUN: llc < %s -mtriple=i686-- -mattr=+prfchw | FileCheck %s -check-prefix=PRFCHWSSE
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; RUN: llc < %s -mtriple=i686-- -mcpu=slm | FileCheck %s -check-prefix=PRFCHWSSE
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; RUN: llc < %s -mtriple=i686-- -mcpu=btver2 | FileCheck %s -check-prefix=PRFCHWSSE
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; RUN: llc < %s -mtriple=i686-- -mcpu=btver2 -mattr=-prfchw | FileCheck %s -check-prefix=SSE
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; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prefetchwt1 | FileCheck %s -check-prefix=PREFETCHWT1
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; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+prefetchwt1 | FileCheck %s -check-prefix=PREFETCHWT1
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; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+3dnow,+prefetchwt1 | FileCheck %s -check-prefix=PREFETCHWT1
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; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow | FileCheck %s -check-prefix=3DNOW
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; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow,+prfchw | FileCheck %s -check-prefix=3DNOW
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; Rules:
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; 3dnow by itself get you just the single prefetch instruction with no hints
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; sse provides prefetch0/1/2/nta
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; supporting prefetchw, but not 3dnow implicitly provides prefetcht0/1/2/nta regardless of sse setting as we need something to fall back to for the non-write hint.
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; supporting prefetchwt1 implies prefetcht0/1/2/nta and prefetchw regardless of other settings. this allows levels for non-write and gives us an instruction for write+T0
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; 3dnow prefetch instruction will only get used if you have no other prefetch instructions enabled
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; rdar://10538297
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define void @t(i8* %ptr) nounwind {
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; SSE-LABEL: t:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; SSE-NEXT: prefetcht2 (%eax)
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; SSE-NEXT: prefetcht1 (%eax)
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; SSE-NEXT: prefetcht0 (%eax)
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; SSE-NEXT: prefetchnta (%eax)
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; SSE-NEXT: prefetcht2 (%eax)
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; SSE-NEXT: prefetcht1 (%eax)
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; SSE-NEXT: prefetcht0 (%eax)
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; SSE-NEXT: prefetchnta (%eax)
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; SSE-NEXT: retl
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;
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; PRFCHWSSE-LABEL: t:
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; PRFCHWSSE: # %bb.0: # %entry
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; PRFCHWSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; PRFCHWSSE-NEXT: prefetcht2 (%eax)
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; PRFCHWSSE-NEXT: prefetcht1 (%eax)
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; PRFCHWSSE-NEXT: prefetcht0 (%eax)
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; PRFCHWSSE-NEXT: prefetchnta (%eax)
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; PRFCHWSSE-NEXT: prefetchw (%eax)
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; PRFCHWSSE-NEXT: prefetchw (%eax)
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; PRFCHWSSE-NEXT: prefetchw (%eax)
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; PRFCHWSSE-NEXT: prefetchw (%eax)
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; PRFCHWSSE-NEXT: retl
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;
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; PREFETCHWT1-LABEL: t:
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; PREFETCHWT1: # %bb.0: # %entry
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; PREFETCHWT1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; PREFETCHWT1-NEXT: prefetcht2 (%eax)
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; PREFETCHWT1-NEXT: prefetcht1 (%eax)
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; PREFETCHWT1-NEXT: prefetcht0 (%eax)
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; PREFETCHWT1-NEXT: prefetchnta (%eax)
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; PREFETCHWT1-NEXT: prefetchwt1 (%eax)
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; PREFETCHWT1-NEXT: prefetchwt1 (%eax)
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; PREFETCHWT1-NEXT: prefetchw (%eax)
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; PREFETCHWT1-NEXT: prefetchwt1 (%eax)
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; PREFETCHWT1-NEXT: retl
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;
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; 3DNOW-LABEL: t:
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; 3DNOW: # %bb.0: # %entry
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; 3DNOW-NEXT: movl {{[0-9]+}}(%esp), %eax
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; 3DNOW-NEXT: prefetch (%eax)
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; 3DNOW-NEXT: prefetch (%eax)
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; 3DNOW-NEXT: prefetch (%eax)
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; 3DNOW-NEXT: prefetch (%eax)
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; 3DNOW-NEXT: prefetchw (%eax)
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; 3DNOW-NEXT: prefetchw (%eax)
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; 3DNOW-NEXT: prefetchw (%eax)
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; 3DNOW-NEXT: prefetchw (%eax)
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; 3DNOW-NEXT: retl
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entry:
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 1, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 2, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
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tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 0, i32 1 )
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ret void
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}
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declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
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