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b825f20a30
Similar to what was recently done for addcarry/subborrow and has been done for rdrand/rdseed for a while. It's better to use two results and an explicit store in IR when the store isn't part of the semantics of the instruction. This allows store->load forwarding to happen in the middle end. Or the store to be removed if its never loaded. Differential Revision: https://reviews.llvm.org/D51803 llvm-svn: 341698
75 lines
2.0 KiB
LLVM
75 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=generic | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=generic | FileCheck %s --check-prefix=X64
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; Verify that we correctly lower ISD::READCYCLECOUNTER.
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define i64 @test_builtin_readcyclecounter() {
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; X86-LABEL: test_builtin_readcyclecounter:
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; X86: # %bb.0:
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; X86-NEXT: rdtsc
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; X86-NEXT: retl
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;
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; X64-LABEL: test_builtin_readcyclecounter:
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; X64: # %bb.0:
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; X64-NEXT: rdtsc
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; X64-NEXT: shlq $32, %rdx
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; X64-NEXT: orq %rdx, %rax
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; X64-NEXT: retq
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%1 = tail call i64 @llvm.readcyclecounter()
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ret i64 %1
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}
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; Verify that we correctly lower the Read Cycle Counter GCC x86 builtins
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; (i.e. RDTSC and RDTSCP).
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define i64 @test_builtin_rdtsc() {
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; X86-LABEL: test_builtin_rdtsc:
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; X86: # %bb.0:
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; X86-NEXT: rdtsc
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; X86-NEXT: retl
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;
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; X64-LABEL: test_builtin_rdtsc:
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; X64: # %bb.0:
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; X64-NEXT: rdtsc
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; X64-NEXT: shlq $32, %rdx
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; X64-NEXT: orq %rdx, %rax
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; X64-NEXT: retq
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%1 = tail call i64 @llvm.x86.rdtsc()
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ret i64 %1
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}
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define i64 @test_builtin_rdtscp(i8* %A) {
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; X86-LABEL: test_builtin_rdtscp:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: .cfi_offset %esi, -8
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: rdtscp
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; X86-NEXT: movl %ecx, (%esi)
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; X86-NEXT: popl %esi
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; X86-NEXT: .cfi_def_cfa_offset 4
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; X86-NEXT: retl
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;
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; X64-LABEL: test_builtin_rdtscp:
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; X64: # %bb.0:
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; X64-NEXT: rdtscp
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; X64-NEXT: shlq $32, %rdx
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; X64-NEXT: orq %rdx, %rax
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; X64-NEXT: movl %ecx, (%rdi)
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; X64-NEXT: retq
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%1 = call { i64, i32 } @llvm.x86.rdtscp()
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%2 = extractvalue { i64, i32 } %1, 1
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%3 = bitcast i8* %A to i32*
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store i32 %2, i32* %3, align 1
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%4 = extractvalue { i64, i32 } %1, 0
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ret i64 %4
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}
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declare i64 @llvm.readcyclecounter()
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declare { i64, i32 } @llvm.x86.rdtscp()
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declare i64 @llvm.x86.rdtsc()
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