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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
24 lines
652 B
LLVM
24 lines
652 B
LLVM
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+xsave | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xsave | FileCheck %s --check-prefix=CHECK64
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define void @test_xsetbv(i32 %in, i32 %high, i32 %low) {
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; CHECK-LABEL: test_xsetbv
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; CHECK: movl 4(%esp), %ecx
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; CHECK: movl 8(%esp), %edx
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; CHECK: movl 12(%esp), %eax
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; CHECK: xsetbv
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; CHECK: ret
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; CHECK64-LABEL: test_xsetbv
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; CHECK64: movl %edx, %eax
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; CHECK64-DAG: movl %edi, %ecx
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; CHECK64-DAG: movl %esi, %edx
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; CHECK64: xsetbv
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; CHECK64: ret
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call void @llvm.x86.xsetbv(i32 %in, i32 %high, i32 %low)
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ret void;
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}
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declare void @llvm.x86.xsetbv(i32, i32, i32)
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