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c5843bab91
These instructions require that the two S registers are adjacent (but not the R registers), because only the first register is included in the encoding, but we were not checking this in the assembler. Differential revision: https://reviews.llvm.org/D44084 llvm-svn: 326696
7 lines
263 B
ArmAsm
7 lines
263 B
ArmAsm
@ RUN: not llvm-mc -triple armv7-eabi < %s 2>&1 | FileCheck %s
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vmov r0, r1, s0, s2
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// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operands must be sequential
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vmov s0, s2, r0, r1
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// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: destination operands must be sequential
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