Alexander Richardson 58a27d4683 Fix .cfi_restore with register numbers > 64 ... Summary: DW_CFA_restore can only encode register numbers up to 64 (6 bits unsigned int). For regsiter numbers > 64 we have to use DW_CFA_restore_extended instead which uses a ULEB128 value. I discovered this problem in the out-of-tree CHERI target since we use DWARF register number 89 for our return capability register. Reviewers: probinson, dblaikie, aprantl, espindola Reviewed By: dblaikie Subscribers: JohnReagan, emaste, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D54420 llvm-svn: 346751		2018-11-13 10:54:49 +00:00
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AArch64	[AArch64] Support HiSilicon's TSV110 processor	2018-11-09 19:32:08 +00:00
AMDGPU	[AMDGPU] support image load/store a16	2018-10-31 10:34:48 +00:00
ARM	[llvm-readelf] Make llvm-readelf more compatible with GNU readelf.	2018-11-12 18:02:38 +00:00
AsmParser	[debuginfo] generate debug info with asm+.file	2018-08-28 16:23:39 +00:00
AVR	[AVR] Redefine the 'SBR' instruction as an alias	2018-09-01 12:22:54 +00:00
BPF
COFF	[COFF] [X86] Don't use llvm_unreachable for unsupported relocation types	2018-10-04 20:43:38 +00:00
Disassembler	[AArch64] Support HiSilicon's TSV110 processor	2018-11-09 19:32:08 +00:00
ELF	Fix .cfi_restore with register numbers > 64	2018-11-13 10:54:49 +00:00
Hexagon	[MC] Fix 3 objdump tests after rL346610	2018-11-11 19:15:27 +00:00
Lanai
MachO	[MC/Dwarf] Unclamp DWARF linetables format on Darwin.	2018-09-13 13:13:50 +00:00
Mips	[mips] Support sigrie instruction	2018-11-06 14:37:24 +00:00
PowerPC	[MC] Avoid inlining constant symbols with variants.	2018-09-17 20:34:26 +00:00
RISCV	[RISCV] Support .option relax and .option norelax	2018-11-12 14:25:07 +00:00
Sparc	[Sparc] Add unimp alias	2018-09-27 12:34:53 +00:00
SystemZ	[SystemZ] Implement SystemZOperand::print()	2018-10-26 00:36:00 +00:00
WebAssembly	[WebAssembly] Added WasmAsmParser.	2018-11-12 20:15:01 +00:00
X86	[MC] Separate masm integer literal lexer support from inline asm	2018-10-24 20:23:57 +00:00