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a8d946115e
In Thumb 1, with the new ADDCARRY / SUBCARRY the scheduler may need to do copies CPSR ↔ GPR but not all Thumb1 targets implement them. The schedule can attempt, before attempting a copy, to clone the instructions but it does not currently do that for nodes with input glue. In this patch we introduce a target-hook to let the hook decide if a glued machinenode is still eligible for copying. In this case these are ARM::tADCS and ARM::tSBCS . As a follow-up of this change we should actually implement the copies for the Thumb1 targets that do implement them and restrict the hook to the targets that can't really do such copy as these clones are not ideal. This change fixes PR35836. Differential Revision: https://reviews.llvm.org/D42051 llvm-svn: 323857
58 lines
1.9 KiB
LLVM
58 lines
1.9 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:e-p:64:64-i128:64-v128:64:128-a:0:64-n64-S64"
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target triple = "thumbv6---gnueabi"
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; Function Attrs: norecurse nounwind readonly
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define i128 @a(i64* nocapture readonly %z) local_unnamed_addr #0 {
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entry:
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%0 = load i64, i64* %z, align 4
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%conv.i = zext i64 %0 to i128
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%arrayidx1 = getelementptr inbounds i64, i64* %z, i64 2
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%1 = load i64, i64* %arrayidx1, align 4
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%conv.i38 = zext i64 %1 to i128
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%shl.i39 = shl nuw i128 %conv.i38, 64
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%or = or i128 %shl.i39, %conv.i
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%arrayidx3 = getelementptr inbounds i64, i64* %z, i64 1
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%2 = load i64, i64* %arrayidx3, align 4
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%conv.i37 = zext i64 %2 to i128
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%arrayidx5 = getelementptr inbounds i64, i64* %z, i64 3
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%3 = load i64, i64* %arrayidx5, align 4
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%conv.i35 = zext i64 %3 to i128
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%shl.i36 = shl nuw i128 %conv.i35, 64
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%or7 = or i128 %shl.i36, %conv.i37
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%arrayidx10 = getelementptr inbounds i64, i64* %z, i64 4
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%4 = load i64, i64* %arrayidx10, align 4
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%conv.i64 = zext i64 %4 to i128
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%shl.i33 = shl nuw i128 %conv.i64, 64
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%or12 = or i128 %shl.i33, %conv.i
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%arrayidx15 = getelementptr inbounds i64, i64* %z, i64 5
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%5 = load i64, i64* %arrayidx15, align 4
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%conv.i30 = zext i64 %5 to i128
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%shl.i = shl nuw i128 %conv.i30, 64
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%or17 = or i128 %shl.i, %conv.i37
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%add = add i128 %or7, %or
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%add18 = add i128 %or17, %or12
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%mul = mul i128 %add18, %add
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ret i128 %mul
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}
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; CHECK: adds r4, r2, r7
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; CHECK: mov r4, r1
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; CHECK: adcs r4, r6
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; CHECK: ldr r4, [sp, #20] @ 4-byte Reload
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; CHECK: adcs r5, r4
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; CHECK: ldr r4, [sp, #24] @ 4-byte Reload
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; CHECK: adcs r3, r4
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; CHECK: adds r4, r2, r7
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; CHECK: adcs r1, r6
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; CHECK: mov r2, sp
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; CHECK: str r4, [r2]
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; CHECK: str r1, [r2, #4]
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; CHECK: ldr r6, [r0, #16]
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; CHECK: ldr r7, [r0, #24]
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; CHECK: adcs r7, r6
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; CHECK: str r7, [r2, #8]
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; CHECK: ldr r6, [r0, #20]
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; CHECK: ldr r0, [r0, #28]
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; CHECK: adcs r0, r6
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