Preston Gurd b1c34fa73f The current Intel Atom microarchitecture has a feature whereby when a function ... returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. Patch by Andy Zhang. llvm-svn: 171524		2013-01-04 20:54:54 +00:00
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ARM	Revert "Adding support for llvm.arm.neon.vaddl[su].* and"	2012-12-20 21:09:38 +00:00
CPP
Generic	After reducing the size of an operation in the DAG we zero-extend the reduced	2012-12-19 07:39:08 +00:00
Hexagon
MBlaze
Mips	[mips] MipsTargetLowering::getSetCCResultType should return a vector type if	2013-01-04 20:06:01 +00:00
MSP430
NVPTX
PowerPC	Support ppcf128 in SelectionDAG::getConstantFP	2012-12-30 19:03:32 +00:00
R600	DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes	2013-01-02 22:13:01 +00:00
SI
SPARC
Thumb
Thumb2	On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,	2012-12-20 19:59:30 +00:00
X86	The current Intel Atom microarchitecture has a feature whereby when a function	2013-01-04 20:54:54 +00:00
XCore