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4554c8ed29
If the DAG already has only legal types, then the second round of DAG combines is skipped. In this case VSELECT+SETCC patterns that match a more efficient instruction (e.g. min/max) are never recognized. This fix allows VSELECT+SETCC combines if the types are already legal before DAG type legalization. Reviewer: Nadav llvm-svn: 190105
114 lines
3.0 KiB
LLVM
114 lines
3.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; CHECK-LABEL: test1
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; CHECK: vcmpleps
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; CHECK: vmovups
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; CHECK: ret
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define <16 x float> @test1(<16 x float> %x, <16 x float> %y) nounwind {
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%mask = fcmp ole <16 x float> %x, %y
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%max = select <16 x i1> %mask, <16 x float> %x, <16 x float> %y
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ret <16 x float> %max
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}
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; CHECK-LABEL: test2
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; CHECK: vcmplepd
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; CHECK: vmovupd
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; CHECK: ret
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define <8 x double> @test2(<8 x double> %x, <8 x double> %y) nounwind {
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%mask = fcmp ole <8 x double> %x, %y
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%max = select <8 x i1> %mask, <8 x double> %x, <8 x double> %y
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ret <8 x double> %max
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}
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; CHECK-LABEL: test3
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; CHECK: vpcmpeqd (%rdi)
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; CHECK: vmovdqu32
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; CHECK: ret
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define <16 x i32> @test3(<16 x i32> %x, <16 x i32> %x1, <16 x i32>* %yp) nounwind {
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%y = load <16 x i32>* %yp, align 4
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%mask = icmp eq <16 x i32> %x, %y
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %x1
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ret <16 x i32> %max
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}
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; CHECK-LABEL: @test4_unsigned
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; CHECK: vpcmpnltud
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; CHECK: vmovdqu32
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; CHECK: ret
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define <16 x i32> @test4_unsigned(<16 x i32> %x, <16 x i32> %y) nounwind {
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%mask = icmp uge <16 x i32> %x, %y
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%max = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %y
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ret <16 x i32> %max
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}
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; CHECK-LABEL: test5
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; CHECK: vpcmpeqq {{.*}}%k1
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; CHECK: vmovdqu64 {{.*}}%k1
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; CHECK: ret
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define <8 x i64> @test5(<8 x i64> %x, <8 x i64> %y) nounwind {
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%mask = icmp eq <8 x i64> %x, %y
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%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %y
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ret <8 x i64> %max
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}
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; CHECK-LABEL: test6_unsigned
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; CHECK: vpcmpnleuq {{.*}}%k1
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; CHECK: vmovdqu64 {{.*}}%k1
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; CHECK: ret
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define <8 x i64> @test6_unsigned(<8 x i64> %x, <8 x i64> %y) nounwind {
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%mask = icmp ugt <8 x i64> %x, %y
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%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %y
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ret <8 x i64> %max
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}
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; CHECK-LABEL: test7
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; CHECK: xor
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; CHECK: vcmpltps
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; CHECK: vblendvps
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; CHECK: ret
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define <4 x float> @test7(<4 x float> %a, <4 x float> %b) {
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%mask = fcmp olt <4 x float> %a, zeroinitializer
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%c = select <4 x i1>%mask, <4 x float>%a, <4 x float>%b
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ret <4 x float>%c
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}
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; CHECK-LABEL: test8
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; CHECK: xor
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; CHECK: vcmpltpd
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; CHECK: vblendvpd
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; CHECK: ret
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define <2 x double> @test8(<2 x double> %a, <2 x double> %b) {
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%mask = fcmp olt <2 x double> %a, zeroinitializer
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%c = select <2 x i1>%mask, <2 x double>%a, <2 x double>%b
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ret <2 x double>%c
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}
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; CHECK-LABEL: test9
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; CHECK: vpcmpeqd
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; CHECK: vpblendmd
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; CHECK: ret
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define <8 x i32> @test9(<8 x i32> %x, <8 x i32> %y) nounwind {
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%mask = icmp eq <8 x i32> %x, %y
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
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ret <8 x i32> %max
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}
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; CHECK-LABEL: test10
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; CHECK: vcmpeqps
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; CHECK: vblendmps
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; CHECK: ret
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define <8 x float> @test10(<8 x float> %x, <8 x float> %y) nounwind {
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%mask = fcmp oeq <8 x float> %x, %y
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%max = select <8 x i1> %mask, <8 x float> %x, <8 x float> %y
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ret <8 x float> %max
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}
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; CHECK-LABEL: test11_unsigned
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; CHECK: vpmaxud
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; CHECK: ret
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define <8 x i32> @test11_unsigned(<8 x i32> %x, <8 x i32> %y) nounwind {
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%mask = icmp ugt <8 x i32> %x, %y
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%max = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
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ret <8 x i32> %max
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}
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