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llvm-mirror/test/CodeGen/AMDGPU/combine_vloads.ll
Yaxun Liu f2debeba3c [AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
r600 uses dummy pointer info for lowering load/store. Since dummy pointer info
assumes address space 0, this causes isel failure when temporary load/store SDNodes
are generated for amdgiz environment.

Since the offest is not constant, FixedStack pseudo source value cannot be used
to create the pointer info. This patch creates pointer info using llvm undef value.
At least this provides correct address space so that isel can be done correctly.

Differential Revision: https://reviews.llvm.org/D39698

llvm-svn: 317862
2017-11-10 02:03:28 +00:00

43 lines
2.0 KiB
LLVM

; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
;
; kernel void combine_vloads(global char8 addrspace(5)* src, global char8 addrspace(5)* result) {
; for (int i = 0; i < 1024; ++i)
; result[i] = src[0] + src[1] + src[2] + src[3];
; }
;
; 128-bit loads instead of many 8-bit
; EG-LABEL: {{^}}combine_vloads:
; EG: VTX_READ_128
; EG: VTX_READ_128
define amdgpu_kernel void @combine_vloads(<8 x i8> addrspace(1)* nocapture %src, <8 x i8> addrspace(1)* nocapture %result) nounwind {
entry:
br label %for.body
for.exit: ; preds = %for.body
ret void
for.body: ; preds = %for.body, %entry
%i.01 = phi i32 [ 0, %entry ], [ %tmp19, %for.body ]
%arrayidx_v4 = bitcast <8 x i8> addrspace(1)* %src to <32 x i8> addrspace(1)*
%0 = bitcast <32 x i8> addrspace(1)* %arrayidx_v4 to <8 x i32> addrspace(1)*
%vecload2 = load <8 x i32>, <8 x i32> addrspace(1)* %0, align 32
%1 = bitcast <8 x i32> %vecload2 to <32 x i8>
%tmp5 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%tmp8 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%tmp9 = add nsw <8 x i8> %tmp5, %tmp8
%tmp12 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
%tmp13 = add nsw <8 x i8> %tmp9, %tmp12
%tmp16 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
%tmp17 = add nsw <8 x i8> %tmp13, %tmp16
%scevgep = getelementptr <8 x i8>, <8 x i8> addrspace(1)* %result, i32 %i.01
%2 = bitcast <8 x i8> %tmp17 to <2 x i32>
%3 = bitcast <8 x i8> addrspace(1)* %scevgep to <2 x i32> addrspace(1)*
store <2 x i32> %2, <2 x i32> addrspace(1)* %3, align 8
%tmp19 = add nsw i32 %i.01, 1
%exitcond = icmp eq i32 %tmp19, 1024
br i1 %exitcond, label %for.exit, label %for.body
}