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f58aee7cea
Summary: Also explicitly port over some tests in llvm.amdgcn.image.* that were missing. Some tests are removed because they no longer apply (i.e. explicitly testing building an address vector via insertelement). This is in preparation for the eventual removal of the old-style intrinsics. Some additional notes: - constant-address-space-32bit.ll: change some GCN-NEXT to GCN because the instruction schedule was subtly altered - insert_vector_elt.ll: the old test didn't actually test anything, because %tmp1 was not used; remove the load, because it doesn't work (Because of the amdgpu_ps calling convention? In any case, it's orthogonal to what the test claims to be testing.) Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf Reviewers: arsenm, rampitec Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D48018 llvm-svn: 335229
63 lines
1.9 KiB
LLVM
63 lines
1.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}else_no_execfix:
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; CHECK: ; %Flow
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; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]],
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; CHECK-NEXT: s_xor_b64 exec, exec, [[DST]]
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; CHECK-NEXT: ; mask branch
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define amdgpu_ps float @else_no_execfix(i32 %z, float %v) #0 {
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main_body:
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%cc = icmp sgt i32 %z, 5
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br i1 %cc, label %if, label %else
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if:
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%v.if = fmul float %v, 2.0
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br label %end
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else:
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%v.else = fmul float %v, 3.0
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br label %end
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end:
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%r = phi float [ %v.if, %if ], [ %v.else, %else ]
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ret float %r
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}
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; CHECK-LABEL: {{^}}else_execfix_leave_wqm:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_mov_b64 [[INIT_EXEC:s\[[0-9]+:[0-9]+\]]], exec
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; CHECK: ; %Flow
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; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]],
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; CHECK-NEXT: s_and_b64 exec, exec, [[INIT_EXEC]]
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; CHECK-NEXT: s_and_b64 [[AND_INIT:s\[[0-9]+:[0-9]+\]]], exec, [[DST]]
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; CHECK-NEXT: s_xor_b64 exec, exec, [[AND_INIT]]
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; CHECK-NEXT: ; mask branch
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define amdgpu_ps void @else_execfix_leave_wqm(i32 %z, float %v) #0 {
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main_body:
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%cc = icmp sgt i32 %z, 5
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br i1 %cc, label %if, label %else
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if:
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%v.if = fmul float %v, 2.0
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br label %end
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else:
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%c = fmul float %v, 3.0
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%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
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%v.else = extractelement <4 x float> %tex, i32 0
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br label %end
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end:
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%r = phi float [ %v.if, %if ], [ %v.else, %else ]
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call void @llvm.amdgcn.buffer.store.f32(float %r, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
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ret void
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}
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declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1
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declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind writeonly }
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attributes #2 = { nounwind readonly }
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