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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
27 lines
812 B
YAML
27 lines
812 B
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-apple-ios -run-pass regallocfast -o - %s | FileCheck %s
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# This test used to crash the fast register alloc.
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# Basically, when a basic block has liveins, the fast regalloc
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# was deferencing the begin iterator of this block. However,
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# when this block is empty and it will just crashed!
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---
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name: crashing
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: crashing
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $x0, $x1
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; CHECK: bb.1:
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; CHECK: renamable $w0 = MOVi32imm -1
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; CHECK: RET_ReallyLR implicit killed $w0
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bb.1:
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liveins: $x0, $x1
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bb.2:
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%0:gpr32 = MOVi32imm -1
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$w0 = COPY %0
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RET_ReallyLR implicit $w0
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...
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