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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
180 lines
5.8 KiB
LLVM
180 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=KNL
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;RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=CHECK --check-prefix=SKX
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define <16 x i32> @shift_16_i32(<16 x i32> %a) {
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; CHECK-LABEL: shift_16_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsrld $1, %zmm0, %zmm0
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; CHECK-NEXT: vpslld $12, %zmm0, %zmm0
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; CHECK-NEXT: vpsrad $12, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%b = lshr <16 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%c = shl <16 x i32> %b, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
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%d = ashr <16 x i32> %c, <i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
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ret <16 x i32> %d;
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}
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define <8 x i64> @shift_8_i64(<8 x i64> %a) {
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; CHECK-LABEL: shift_8_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsrlq $1, %zmm0, %zmm0
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; CHECK-NEXT: vpsllq $12, %zmm0, %zmm0
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; CHECK-NEXT: vpsraq $12, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%b = lshr <8 x i64> %a, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
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%c = shl <8 x i64> %b, <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
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%d = ashr <8 x i64> %c, <i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12, i64 12>
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ret <8 x i64> %d;
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}
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define <4 x i64> @shift_4_i64(<4 x i64> %a) {
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; KNL-LABEL: shift_4_i64:
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; KNL: # %bb.0:
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; KNL-NEXT: vpsrlq $1, %ymm0, %ymm0
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; KNL-NEXT: vpsllq $12, %ymm0, %ymm0
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; KNL-NEXT: vpsraq $12, %zmm0, %zmm0
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; KNL-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
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; KNL-NEXT: retq
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;
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; SKX-LABEL: shift_4_i64:
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; SKX: # %bb.0:
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; SKX-NEXT: vpsrlq $1, %ymm0, %ymm0
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; SKX-NEXT: vpsllq $12, %ymm0, %ymm0
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; SKX-NEXT: vpsraq $12, %ymm0, %ymm0
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; SKX-NEXT: retq
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%b = lshr <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%c = shl <4 x i64> %b, <i64 12, i64 12, i64 12, i64 12>
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%d = ashr <4 x i64> %c, <i64 12, i64 12, i64 12, i64 12>
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ret <4 x i64> %d;
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}
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define <8 x i64> @variable_shl4(<8 x i64> %x, <8 x i64> %y) {
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; CHECK-LABEL: variable_shl4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllvq %zmm1, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%k = shl <8 x i64> %x, %y
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ret <8 x i64> %k
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}
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define <16 x i32> @variable_shl5(<16 x i32> %x, <16 x i32> %y) {
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; CHECK-LABEL: variable_shl5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllvd %zmm1, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%k = shl <16 x i32> %x, %y
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ret <16 x i32> %k
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}
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define <16 x i32> @variable_srl0(<16 x i32> %x, <16 x i32> %y) {
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; CHECK-LABEL: variable_srl0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsrlvd %zmm1, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%k = lshr <16 x i32> %x, %y
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ret <16 x i32> %k
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}
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define <8 x i64> @variable_srl2(<8 x i64> %x, <8 x i64> %y) {
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; CHECK-LABEL: variable_srl2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsrlvq %zmm1, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%k = lshr <8 x i64> %x, %y
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ret <8 x i64> %k
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}
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define <16 x i32> @variable_sra1(<16 x i32> %x, <16 x i32> %y) {
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; CHECK-LABEL: variable_sra1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsravd %zmm1, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%k = ashr <16 x i32> %x, %y
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ret <16 x i32> %k
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}
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define <8 x i64> @variable_sra2(<8 x i64> %x, <8 x i64> %y) {
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; CHECK-LABEL: variable_sra2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsravq %zmm1, %zmm0, %zmm0
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; CHECK-NEXT: retq
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%k = ashr <8 x i64> %x, %y
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ret <8 x i64> %k
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}
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define <4 x i64> @variable_sra3(<4 x i64> %x, <4 x i64> %y) {
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; KNL-LABEL: variable_sra3:
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; KNL: # %bb.0:
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; KNL-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
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; KNL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
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; KNL-NEXT: vpsravq %zmm1, %zmm0, %zmm0
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; KNL-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
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; KNL-NEXT: retq
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;
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; SKX-LABEL: variable_sra3:
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; SKX: # %bb.0:
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; SKX-NEXT: vpsravq %ymm1, %ymm0, %ymm0
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; SKX-NEXT: retq
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%k = ashr <4 x i64> %x, %y
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ret <4 x i64> %k
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}
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define <8 x i16> @variable_sra4(<8 x i16> %x, <8 x i16> %y) {
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; KNL-LABEL: variable_sra4:
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; KNL: # %bb.0:
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; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
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; KNL-NEXT: vpmovsxwd %xmm0, %ymm0
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; KNL-NEXT: vpsravd %ymm1, %ymm0, %ymm0
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; KNL-NEXT: vpmovdw %zmm0, %ymm0
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; KNL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; KNL-NEXT: retq
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;
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; SKX-LABEL: variable_sra4:
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; SKX: # %bb.0:
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; SKX-NEXT: vpsravw %xmm1, %xmm0, %xmm0
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; SKX-NEXT: retq
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%k = ashr <8 x i16> %x, %y
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ret <8 x i16> %k
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}
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define <16 x i32> @variable_sra01_load(<16 x i32> %x, <16 x i32>* %y) {
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; CHECK-LABEL: variable_sra01_load:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsravd (%rdi), %zmm0, %zmm0
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; CHECK-NEXT: retq
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%y1 = load <16 x i32>, <16 x i32>* %y
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%k = ashr <16 x i32> %x, %y1
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ret <16 x i32> %k
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}
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define <16 x i32> @variable_shl1_load(<16 x i32> %x, <16 x i32>* %y) {
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; CHECK-LABEL: variable_shl1_load:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllvd (%rdi), %zmm0, %zmm0
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; CHECK-NEXT: retq
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%y1 = load <16 x i32>, <16 x i32>* %y
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%k = shl <16 x i32> %x, %y1
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ret <16 x i32> %k
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}
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define <16 x i32> @variable_srl0_load(<16 x i32> %x, <16 x i32>* %y) {
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; CHECK-LABEL: variable_srl0_load:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsrlvd (%rdi), %zmm0, %zmm0
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; CHECK-NEXT: retq
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%y1 = load <16 x i32>, <16 x i32>* %y
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%k = lshr <16 x i32> %x, %y1
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ret <16 x i32> %k
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}
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define <8 x i64> @variable_srl3_load(<8 x i64> %x, <8 x i64>* %y) {
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; CHECK-LABEL: variable_srl3_load:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsrlvq (%rdi), %zmm0, %zmm0
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; CHECK-NEXT: retq
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%y1 = load <8 x i64>, <8 x i64>* %y
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%k = lshr <8 x i64> %x, %y1
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ret <8 x i64> %k
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}
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