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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
65 lines
1.8 KiB
LLVM
65 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=corei7 | FileCheck %s
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declare i8 @llvm.ctpop.i8(i8) nounwind readnone
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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define i32 @test1(i64 %x) nounwind readnone {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: leaq -1(%rdi), %rcx
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testq %rcx, %rdi
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; CHECK-NEXT: setne %al
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; CHECK-NEXT: retq
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%count = tail call i64 @llvm.ctpop.i64(i64 %x)
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%cast = trunc i64 %count to i32
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%cmp = icmp ugt i32 %cast, 1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @test2(i64 %x) nounwind readnone {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: leaq -1(%rdi), %rcx
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testq %rcx, %rdi
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%count = tail call i64 @llvm.ctpop.i64(i64 %x)
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%cmp = icmp ult i64 %count, 2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @test3(i64 %x) nounwind readnone {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: popcntq %rdi, %rcx
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; CHECK-NEXT: andb $63, %cl
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: cmpb $2, %cl
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; CHECK-NEXT: setb %al
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; CHECK-NEXT: retq
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%count = tail call i64 @llvm.ctpop.i64(i64 %x)
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%cast = trunc i64 %count to i6 ; Too small for 0-64
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%cmp = icmp ult i6 %cast, 2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i8 @test4(i8 %x) nounwind readnone {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andl $127, %edi
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; CHECK-NEXT: popcntl %edi, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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%x2 = and i8 %x, 127
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%count = tail call i8 @llvm.ctpop.i8(i8 %x2)
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%and = and i8 %count, 7
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ret i8 %and
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}
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